Hello!
I'm trying to output PAL signal via digital pins and i got this:
As you can see, there are a blue line and black area on the right. What may cause it?
There is code:
static void davinci_enc_set_pal(struct vid_enc_mode_info *mode_info)
{
enableDigitalOutput(0);
if (cpu_is_davinci_dm355()) {
dispc_reg_out(VENC_CLKCTL, 0x1);
dispc_reg_out(VENC_VIDCTL, 0);
// DM350 Configure VDAC_CONFIG
__raw_writel(0x0E21A6B6, IO_ADDRESS(DM3XX_VDAC_CONFIG));
} else if (cpu_is_davinci_dm365()) {
dispc_reg_out(VENC_CLKCTL, 0x1);
dispc_reg_out(VENC_VIDCTL, 0);
__raw_writel(0x081141CF, IO_ADDRESS(DM3XX_VDAC_CONFIG));
} else {
// to set VENC CLK DIV to 1 - final clock is 54 MHz
dispc_reg_merge(VENC_VIDCTL, 0, 1 << 1);
// Set REC656 Mode
dispc_reg_out(VENC_YCCCTL, 0x1);
}
/*
dispc_reg_merge(VENC_SYNCCTL, 1 << VENC_SYNCCTL_OVD_SHIFT,
VENC_SYNCCTL_OVD);
*/
osd_write_left_margin(mode_info->left_margin + 100);
// PAL display shows shakiness in the OSD0 when
//this is set to upper margin. Need to bump it
// by 2 in the case of DM365
if (cpu_is_davinci_dm365())
osd_write_upper_margin(mode_info->upper_margin + 2);
else
osd_write_upper_margin(mode_info->upper_margin);
dispc_reg_merge(VENC_VMOD, VENC_VMOD_VENC, VENC_VMOD_VENC);
dispc_reg_out(VENC_DACTST, 0x0);
/* set VPSS clock */
__raw_writel(0x18, IO_ADDRESS(SYS_VPSS_CLKCTL)); //enabling VPBE clock and DAC clock
/* VPBE PINMUX */
unsigned int temp = 0;
void __iomem *pinmux1 = (void __iomem *) IO_ADDRESS(0x01C40004);
temp = __raw_readl(pinmux1); //select VCLKL and HVSYNC
temp &= ~(0x01 << 22); //VCLK Enable
__raw_writel(temp, pinmux1);
printk("Ev NTSC out, GPIO PINMUX1 Set Value: 0x%08X\n", temp);
//YCC8 BT.656
dispc_reg_out(VENC_CLKCTL, 0x111);
//OSD Set
__raw_writel(mode_info->left_margin,
IO_ADDRESS(DM365_OSD_REG_BASE + OSD_BASEPX));
__raw_writel(mode_info->upper_margin,
IO_ADDRESS(DM365_OSD_REG_BASE + OSD_BASEPY));
dispc_reg_out(VENC_VIDCTL, 0x6000);
dispc_reg_out(VENC_DCLKCTL, 0x005);
dispc_reg_out(VENC_DCLKPTN0, 0x13);
davinci_enc_set_display_timing(mode_info);
dispc_reg_out(VENC_SYNCCTL, (VENC_SYNCCTL_SYEV | VENC_SYNCCTL_SYEH | VENC_SYNCCTL_HPL | VENC_SYNCCTL_VPL)); //?
dispc_reg_out(VENC_VMOD, 0x1041); //1001 - ntsc, 1041 - pal,1051 - non standrt timing, 1043 - pal and normal composite output
dispc_reg_out(VENC_YCCCTL, 0x13);}
