Hi everybody ,
about DDR3 compensation mechanism (write/read leveling) by AM335x.
We are connecting the AM3358 to a single Micron MT41J64M16JT-125 DDR chip, the same configuration of the TMDSSK3358 (starter kit).
To ease the routing process, normally it is possible to swap the assignment of DQx (data) between the host processor and the memory chip.
This is what is done in the starter kit.
We will probably 'copy' exactly the routing for the DDR3 for this board, but looking to the schematic I noticed that DDR_D3 from Sitara is connected to D0 on the DDR3 chip.
For Micron MT41J64M16JT-125 DDR, the DQ0 and DQ8 from the DDR3 chip are used to feedback to the memory controller (inside AM335x) the feedback clock to perform the calibration procedure.
For this reason I found onother architectures that it was allowed to swap the DQx data except DQ0 and DQ8.
So my question is:
# Is the write leveling calibration performed normally by AM335x?
# If YES, how is performed? Is the starter kit scheme compatible?
Thank you very much in advance
bye
Carlo
