Hello,
I'm working with a custom board with C6657 and two DDR3 memories of type MT41J128M16HA-125IT:D the same as C6657 EVM board.
The custom board also makes connection the same as C6657 EVM board
The issues are that C6657 could not access DDR3 correctly with status below.
DDR3_STATUS :
Indicates read DQS gate training has timed out
Read data eye training has timed out
Write Leveling Success
I use evmc6657l_custom.gel which have been set the PHY and registers following DDR3 initialization guide (refer to accessories) to test DDR3.
LOG:
C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output:
Connecting Target...
C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6657L GEL file Ver is 1.003
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL not in Bypass, Enable BYPASS in the PLL Controller...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=12, md=4!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR3 Init begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR3 Init done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed
C66xx_0: GEL Output: first DDR3 ADDR: 0x80000000 // It will be correct when first DDR3 ADDR = first DDR3 VALUE
C66xx_0: GEL Output: first DDR3 VALUE: 0x00446000 // failed
Here are the questions:
1 How do I deal with read DQS gate training time out and Read Data eye training time out?
2 I set the average of Differential Pair routing length to Stripline length and set 0 to Microstrip length. Is it correct?
3 I set the Device and speed grade in Registers excel User Defined with values selected from Datasheet of MT41J128M16HA-125IT:D. And Registers will be the same as C6657 evm board I figured. But it's different.
This is my first time to use DDR3. Could you help me solve these issues?
Thank you in advance.
regards,
bai
