I'm wokring on debugging a DDR3 PHY timing issue. We use the SW leveing procedure as described in the following wiki
http://processors.wiki.ti.com/index.php/TI814x-DDR3-Init-U-Boot
The problme we have is, when we calculate the seed values using the spreadsheet, we get negative values for two of the WR DQS seed values. This is because on two of the byte lanes, CK trace is longer than DQS trace but on the other two byte lanes CK trace is shorter than DQS trace. The documents say in one case we invert the CK signal but in the other case not to invert the clock. The problem is we have both cases but yet the clock invert is global to all four lanes. If we do invert the clock, we get positive values for all the seeds values but when we run this through the leveling algorithm on tghe target, the resulting values produce many DDR errors. We get much better results if we use the seed values with the clock invert set to 1 but then we don't actually invert the clock in the final uboot/GEL settings. But we still get some errors.
My question is, where can I get the source code to the SW leveling algorithm that runs on the target, in this case, it's the source to the file DDR3_SlaveRatio_ByteWiseSearch_TI814x.out? I'd like to see how it determines the min and max values for each of the RD/WR/ and DQS ratio values and how sensitive it is to the seed values.
