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two Ethernet ports with GPMC in AM335x

Nitesh Singh
Intellectual 320 points

I am designing a board using AM335x, where we intend to use the two Ethernet ports in MII mode and also use a 8 bit NAND Flash.  While using the pin mux utility to achieve the desired configuration,  I came across conflict of two pins of GPMC with MII2 .  WAIT0 and WPN are in conflict with mii2_crs and mii2_rxer.  I also found that there is no other pin assigned for them .  

So , how do i resolve this conflict ?? Also , on a broader sense , how do i configure AM335X to use ethercat  and also have a 8 bit NAND Flash , can it be done ??

  • 0
    TI__Guru 62955 points

    The AM335x Silicon Errata has a usage note that describes this limitation.

    If you look at the latest AM335x data sheet, you can see where enhancements to silicon revision 2.0 added the RMII2_CRS_DV signal function to two other terminals.  This was done to allow NAND and RMII2 to be used at the same time.  I realize you were planning to use MII PHYs, but you may need to reconsider and use RMII PHYs.

    If you decide to use RMII rather than MII, please read Advisory 1.0.16.  When using RMII the 50MHz reference clock needs to be sourced by the respective PHY or a low jitter 50MHz clock source. 

    Regards,
    Paul  

     

  • 0
    TI__Mastermind 44306 points

    Nitesh,

    for the question on pin-mux for EtherCAT (here you need the two PRU MIIs) and 8 bit Flash I suggest you have a look at our IDK schematics as a reference. See the 'More literature' section on the link. Details on the software pin-mux for this can be found in the IA-SDK EtherCAT slave examples.

    Regards.

  • 0 in reply to peaves
    Intellectual 320 points

    Hi Paul,

    Thanks for the reply. I got what you are saying. But Ethercat needs MII mode in both the ethernets and we plan to use ethercat alongside 8 bit NAND Flash. So using RMII will not solve the problem ?? 

    Either I am missing something on Ethercat or is it not possible to have the mentioned configuration ?? 

    Thanks,

  • 0 in reply to Nitesh Singh
    TI__Mastermind 44306 points

    Nitesh,

    if you want to implement the EtherCAT slave solution from TI based on PRU-ICSS you need to follow the IA-SDK and related boards (ICE and IDK). Here we do not use the CPSW MII or RMII pins. Instead there are independent MIIs for the PRU subsystem. The integrated switch which can be used for standard Ethernet does not support the cut-through requirements of an EtherCAT slave. If you just need master then the normal switch could be used.

    Regards.

  • 0 in reply to Frank Walzer
    Intellectual 320 points

    Frank Sir,

    Thank you for the reply. I will follow the IDK implementation thoroughly .  But on the point , using MII0 PRU and MII1 PRU along with GPMC , 2 pins still have conflict. 

    I will see what has been done in IDK and then try to reframe my query if it is not solved. 

    Thanks,

  • 0 in reply to Nitesh Singh
    TI__Mastermind 44306 points

    Nitish,

    yes, you are correct. We also had to work-around that issue and it was one reasons for the pin-mux changes in PG2.0. I don't think we have new schematics yet that would show a solution with the new PG2.0 pin-mux possibilities. I suggest you work with your local FAE on a detailed pin-mux scheme for your intended application.

    Regards.