Custom Board DDR3 init

I disassembled DDR3_SlaveRatio_ByteWiseSearch_TI816x.out, and found that after turning off interleaving DDR3 EMIF0 and EMIF1 work correct.

Which is better to use the values ​​for registers  DMM_LISA_MAP_xx ?  I use 2GB memory per 1G on EMIFx (MT41G08M256-125 x 8) , DM8168 chip revision 1.1

Hello,

I understand that you are using only one of the two DDR3 controllers, is that correct? Are you using DDR3_0 (EMIF0) or DDR3_1 (EMIF1)? What is the DDR3 memory size that you are using on your custom board?

For example, on the TI 816x/389x EVM, we have both DDR3 controllers used, we have 4 memory chips attached to DDR3_0 and 4 memory chips attached to DDR3_1. The total DDR3 memory size is 1GB (8 memory chips x 1Gb each).

Refer to the following wiki page, for how to program the DMM_LISA_MAP_x registers:

http://processors.wiki.ti.com/index.php/EZSDK_Memory_Map

Regards,

Pavel

Thanks for the reply.

We use 2 GByte of memory on our board. Eight memory chips by 2Gb each.

After reading the article became clear memory organization.
If I want to use the memory of the mute inteliving DDR3 I must make the following settings?

DMM_LISA_MAP__0 = 0
DMM_LISA_MAP__1 = 0
DMM_LISA_MAP__2 = 0x80600100
DMM_LISA_MAP__3 = 0xC0600200

And I am confused by what I found in the file of evm.c
u-boot-2010.06-psp04.04.00.01

/ * Program the DMM to for interleaved configuration * /
__raw_writel (0x0, DMM_LISA_MAP__0);
__raw_writel (0x0, DMM_LISA_MAP__1);
__raw_writel (0x80640300, DMM_LISA_MAP__2);
__raw_writel (0xC0640320, DMM_LISA_MAP__3);
Following code programs the LISA registers for 2GB physical memory (default configuration).

But it EVM ti816x has only 1GB of memory, or it does not matter, and memory uses addresses from 0x80000000 to 0xC0000000, and others simply are not available