Hi,
according to the datasheet the max bit clock of McBSP in opp100 is high, 48MHz for McBSP 1-4 and 32MHz for McBSP5. So about 20ns and 31ns period.
But there is a wide range for the delay from the bit clock edge and frame/data valid on the tx side (0.6-14ns). This makes it impossible to meet to setup and hold timings on the receive side at full speed: even inverting the polarity of the bit clock on the rx side, the delay above is larger that half clock period. And we cannot work with a bit clock higher than 10-15MHz realistically.
Am I correct?
What is the reason for such a wide range for the "delay time, mcbsp_clkx actve edge to dx and fsx valid"?
Best regards
Massimo