Hi,
I am trying to transmit a stream of data using McBSP module in Am387x Sitara ARM processor. This stream of datas is intend to program an external Altera FPGA. The clock is internally generated and is driven on CLKX pin. Data transfer starts with LSB first. Transmit word length is 16 bits and frame length is 1 word/frame. Frame period is 16 CLKG periods. The clock is enabled (CLKXM bit in PCR register is set to 1) only after the 1st data word has been written in the DXR_REG. There are no "Transmit synchronization" errors during the data transmission.
However, the first byte of data appearing on the DX pin is delayed with respect to clock which cause problem in the FPGA programmation. That is, there is a delay of 8 to 24 clock pulses between the 1st rising clock pulse on the CLKX pin and the 1st data bit on the DX pin. This period is represent between the 2 cursors in the attached screenshot and equal to 17 clock cycles... The first valid byte is 55h in the attached screen shot and starts right after the second cursor
How can I align the 1st bit of data with the first clock pulse?
Here is my McBSP configuration: SPCR2: 0x00c3
SPCR1: 0x0000
RCR2: 0x0000
RCR1: 0x0000
XCR2: 0x0008
XCR1: 0x0040
SRGR2: 0x300f
SRGR1: 0x0e20
PCR0: 0x0c00
XCCR: 0xc808
