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PCIe in DSPC6678, the maximum data payload

Delared Delared
Expert 1945 points

Hi,

Purpose: Communication PCIe between 2 DSPC6678

In the header of TLPs packet I found that:

The data payload length of a transmitted (or received) TLPs must not exceed the length specified by the value in the Max_Payload_Size field of the Transmitter’s  (or receiver’s ) Device Control register.

And the maximum length of data payload in PCie standard is 1024DW

But, In PCIe User Guide [Features], it’s mentioned that:

-  Maximum outbound payload size of 128bytes

- Maximum inbound payload size of 256 bytes.

- The limit on transaction size on the internal bus interface is 128 bytes.

Questions: What is the maximum data payload that I can transfer between 2 DSPs? and it will be done in 1 transaction/TLP Packet or more than one???

For example I want to copy 1048 Byte from Mem1[add 0-0 0004h] to Mem2[ add 0-0 0008h] , what are the main configurations and setting that I need to do ( specially max_data_payload )

Thank’s

  • 0
    TI__Genius 12065 points

    The data payload we are talking about is the payload size of single TLP. The PCIe will break out large data transfer into multiple packets (TLPs), each TLP will hold the payload size no more than the maximum payload size it supports.

    The 1024DW is the maximum size could be supported in PCIe standard protocol. Each individual PCIe device may have its own configuration, such as 128B, 256B, etc. For C667x device, the maximum payload size is as what mentions in the PCIe user guide (128B for outbound and 256B for inbound).

    The payload size also depends on the master which pushes the data into PCIe. Since PCIe does not have its own built-in DMA in C667x, the user could use CorePac or EDMA to push the data into the PCIe data space for the transfer. If we use CorePac, the maximum payload size in each TLP may be only 32 bits (4 bytes) or 64 bits (8 bytes). If we use EDMA, the maximum payload size in TLP will depend on the Data Burst Size (DBS) of the EDMA TC you are choosing. If the DBS=128B, the payload size in each TLP will be 128B, if DBS=64, the payload size will be 64B, etc. Please refer to the section 2.3 in PCIe use case document.

    In your example, the 1048B will be broke into multiple TLPs. For example, if you are using EDMA with DBS=128B, 1048B will be 8 TLPs with payload size 128B and another one TLP with payload size 24B.

    For two DSP test setup, you can simply use the default setup of the maximum payload size in PCIe configuration, which is 128B.

  • 0 in reply to Steven Ji
    Genius 3715 points

    Hi Steven,

    just a small correction: I think the maximum payload size for CorePac is 64 bit / 8 bytes (STDW, STNDW).

    Ralf

  • 0 in reply to Ralf Goebel
    TI__Genius 12065 points

    Ralf,

    I think you are right. I updated my previous post. Thanks for the correction.