DM8168 MAINPLL_FREQ4 default value is 9.333333 ?

n-Houtteilip

Is there a reason the divider (MAINPLL_FREQ4) is set to 9.333333 by default and not 9.216 ?

Section "1.16.1.2.9 Main PLL Frequency 4 Register (MAINPLL_FREQ4)" of SPRUGX8-May 2012 states:

The default FREQ4 value is 9.333333 to generate a 500 MHz SYSCLK4.

And yet in the calculation in Table 1-77 SYSCLK4=493.7143MHz (9.333333) eventhough SYSCLK24=125MHz (MAINPLL_FREQ5 -> 9.216)

Is there issue with assigning 9.216 to MAINPLL_FREQ4 ?

over 12 years ago

0 Pavel Botev over 12 years ago

TI__Guru**** 170625 points

Hello,

The TRM is giving the rounded value of SYSCLK4, the real value is 493714554 Hz. And this is achieved with the 9.333333 value, MAINPLL_FREQ4 register has the value of 0x9955554F.

What is the issue with the 9.333333 value, do you need other (than 493714554) frequency for the SYSCLK4? If yes, what frequency do you need?

Regards,

Pavel

0 n-Houtteilip over 12 years ago in reply to Pavel Botev

Prodigy 220 points

It's more curiosity, I can set it to 9.216, I'm just questioning why this clock divider is preset to obtain 493714554 and not 500000000.

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DM8168 MAINPLL_FREQ4 default value is 9.333333 ?