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Periodic RTI interrupt problem

honghui Qi
Intellectual 380 points

Hi,

I try to configure TI DSP 6727  to generate periodic RTI interrupt. I configured compare 1 with FRC 1 to generate INT1. I only get one interrupt. I observed the RTI registers values and find RTIINTFLAG =2 always. It does not cleared automatically when the INT5 is serviced. If I manually set ISR = 0x20 from watch window, I can get second interrupt. My guess the problem is on the RTIINTFLAG is not cleared after serviced, resulting in no trig on CPU interrupt, since IFR = 0 always after first interrupt is serviced. Do I need to clear RTI register (looks no reg for me to clear the status) in ISR route for continue interrupt like dmax?

Thanks

  • 0
    TI__Genius 14965 points

    Hi,

    That is the usual practice to clear interrupt flag bit triggered in the ISR routine. So that you can prepare for the next interrupt event.

    Regards,

    Hyun

  • 0 in reply to Hyun Kim
    TI__Guru* 84110 points

    Honghui Qi,

    Please refer to the C672x CSL API Reference Guide to find the CSL_rtiHwControl() function. The commands available for this function are listed in the CSL_RtiHwControlCmd enum, one of which is the command CSL_RTI_CMD_CLEAR_INT1.

    You may find an example in the intc example that comes with the C672x CSL for the INTC module. Look for the file intc_example.c and the comp1Isr() ISR example function.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 380 points

    Thanks Randy and Hyun,

    Actually I do not know which register shall I use to clear the interrupt flag. I tried Rtiregs->RTICLEARINT = 0x02 in my ISR, but it then disabled the interrupt, because RtiRegs->RTISETINT  = 0; then I added RtiRegs->RTISETINT = 0x02, after I did Rtiregs->RTICLEARINT = 0x02 So I got many interrupts, which is not my interrupt period designed.

    I do not use CSL library in my program, But I looked at the CSL_rtiHWControl() source code, the command CSL_RTI_CMD_CLEAR_INT1 can clear the interrupt, it is a case statement and call CSL_rtiClearInt1 (hRti) function, but I can not find the source code of CSL_rtiClearInt1 (hRti). you may post the source codes of this function, so I know how it works.

    Thanks

    Honghui

     

     

  • 0 in reply to honghui Qi
    Intellectual 380 points

    It works now. It needs to clear RtiRegs->RTIINTFLAG = 0x02. But in the data sheet,  this register is read only. oh it says RCP-0. What is the P stands for?

    Thanks

    Honghui

  • 0 in reply to honghui Qi
    TI__Guru* 84110 points

    Honghui,

    The C means it can be used to clear, so my guess is the P means with a Positive write to the bit. In some documents we call that W1C meaning Write 1 to Clear.

    Perhaps we can find someone to answer this. I would like to know the exact meaning, too. And that should be written in the document.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 380 points

    Randy,

    Thanks. Appreciated for the help

    Honghui

  • 0 in reply to honghui Qi
    TI__Genius 14965 points

    Hi,

    P means privileged or protected write.

    Regards,

    Hyun

  • 0 in reply to Hyun Kim
    TI__Guru* 84110 points

    Hyun,

    What does that mean for the C6727B?

    Searching the CPU & Instruction Set RG, the datasheet, and the RTI UG for supervisor, privilege, or protect, I found no matches in any of them.

    Is that a property that comes from other architectures that use this module, while the C6727B has privileged / protected status at all times?

    Regards,
    RandyP