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DM368 NOR Boot setting problem

Hennessy
Intellectual 920 points

Dear all

 

My system is :

  CPU : DM368 -- 432MHz

  OS : Non OS

  Flash Memory : Both NAND and NOR

 

Using NAND BOOT Setting : BTSEL[2:0] = 000, AECFG[2:0] = 0xx , CCS5.0 and GEL file(evmdm368.gel) , download my application to DDR and runs well

but Using AEMIF Boot Setting : BTSEL[2:0] = 001, AECFG[2:0] = 101 , same CCS and GEL file, download my application code to DDR and runs fail.

My application code is almost same as diagnostic code of DM368_IPNC_MT5 and used both case.

In fail case, if i disabled all interrupt at boot.asm like below, it runs OK!! 

  

;*------------------------------------------------------  

;* Enable IRQ and FIQ  

;*------------------------------------------------------

 ;MRS     r0, cpsr  

;BIC     r0, r0, #0xC0  ; Enable IRQ and FIQ  

;NOP  

;NOP  

;MSR     cpsr, r0

 

So i doubt about interrupt processing mechanism of both case, NAND and NOR boot hardware setting.

Thanks in advance.

 

 

 

 

 

 

 

 

  • 0
    Intellectual 920 points

    Dear all

     

    I think this problem is related to the location of IVT(Interrupt Vector Table)

    When occurred IRQ, system jumped to 0x02000018 instead 0x00000018.

    Below image is the document about ARM Sub system's Interrupt controller.

    My question is, How can i set or reset VINTH signal.

    Thanks in advance.