Questions when tuning 8168's DDRIII phy.

This type of error occurs when CCS loads the image file .out as it attempt to find the source file associated with the symbol main() so that you can single step through C source.

However, the C source was not provided with these utilities.

You should be able to ignore this message.

Thank you,Azbell.

And accroding to the wiki page,there wil be a print information: such as

Running the Slave Ratio Search Program

Run: 

Enter 0 for DDR Controller 0 & 1 for DDR Controller 1 

0 

Above message doesn't appear in CCS console.Does these appear through UART?

You should see the print in CCS console not in UART>.Did you press F8 to run the application after loading ? Make sure DDR interleaving is disabled and DDR configuration is done correctly by means of GEL file.Did you get any error msgs when loading the out file ?

thank you very much!

When I press the "F8",it works.

But there are some unexpected information in console.

[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE
[CortexA8] RD DQS GATE RATIO MINIMUM VALUE DIDN'T CONVERGE

I calcuate DDR at 800M clock rate.

But it still get the timing value.

Does these timing information  will  be right?

sorry that I didn't describe my setting rigorously.

I entered 796MHz in the ratioseed excel to get the value.

So why does these "DIDN'T CONVERGE " information appear?

the above is my excel.

thank you very much.

"the problem" you mean what?unpected console information or DDR can't run at 1600MHz?

I suspected there are some issues for excel value so I didn't try.

Right now I'll try makeing DDRIII run at 1600MHz. 

This sheet is for EMIF0,and I have another excel sheet for EMIF1.
Both these have the "non-converging" problem.But both at last the Program will get the min/opt/max value for DDRIII run at 1600MHz.

Did you disable EMIF interleaving before you ran the SW leveling out file ?

NO.how to disable EMIF inerleaving by using CCS?

In TI816x_DDR3.gel, change

EMIF4PRCM() {

  WR_MEM_32(DMM_LISA_MAP__0, 0x80640300); /* Interleaved 1GB section from 0x80000000*/
  WR_MEM_32(DMM_LISA_MAP__1, 0xC0640320); /* Interleaved 1GB section from 0xC0000000*/

  WR_MEM_32(DMM_LISA_MAP__2, 0x80640300);
  WR_MEM_32(DMM_LISA_MAP__3, 0xC0640320);

to

  WR_MEM_32(DMM_LISA_MAP__0, 0x80500100);

  WR_MEM_32(DMM_LISA_MAP__1, 0xC0500120);

 
  /*Program the DMM to Access EMIF1*/

  WR_MEM_32(DMM_LISA_MAP__2, 0xA0500200);

  WR_MEM_32(DMM_LISA_MAP__3, 0xE0500220);

Make sure you close and reopen CCS and redo the procedure after modifying the GEL.

Hi:emf

as you say the gel file need to  "disable EMIF inerleaving" ,

why this have been done?

another question is that in my board there are different CLK trace and DQS trace inside every emif (0,1),

how long usually i can regard the size has no effect to use the same opt value for each emif ?

or how i get the opt value for all the ddr chip then?

best regards

xavier