AM3359 GPMC issue

eugenio

Hi all.

When accessing (both read or write) an external FPGA connected through GPMC the CPU get stuck. Jtag emulator (onboard FT2232, schematic cut&paste from ICE demoboard) is unable to halt CPU, and error console shows this error:

CortxA8: Trouble Halting Target CPU: (Error -2062 @ 0x1FE) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.0.899.0)

What does this message means? These are the test conditions:

- for loop writing zeros to fpga, 64 times, starting from address 0x08000000, address incremented every write:

...

volatile unsigned short int *data;

data=(volatile unsigned short int*)0x08000000;

for (index=0; index<64; index++)

{

data[index]=0x0000;

}

...

- FPGA is not programmed yet, so every pin is tristated;

- I can see one single bus access (\CS, ALE and \WR signal tranisions at expected timings) then CPU/Jtag stop responding.

- the same application, running on ICE demoboard, works fine... I can see all signals swinging with exact timings as expected.

Please, help!

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Hi Eugenio,

Could it be something to do with the GPMC WAIT signal? Check to see that it's disabled in GPMC configuration.

0 eugenio over 12 years ago in reply to Biser Gatchev-XID

Expert 1505 points

Thank you!

I've checked and it was not properly configured. GPMC must NOT monitorate wait signal.

I've updated the init code but with no effect: issue is still here.

Attached you can find init code called before accessing the external fpga:

Fullscreen 6136.gpmc__init_code.c Download

....


unsigned int fpga_ram_PinMuxSetup(void)
{
    unsigned int status = FALSE;

	GPMCClkConfig();

	/* GPMC_AD0 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(0)) =
	( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT);
	/* GPMC_AD1 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(1)) =
	( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT)|
	( 0 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT) ;
	/* GPMC_AD2 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(2)) =
	( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT)|
	( 0 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT) ;
	/* GPMC_AD3 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(3)) =
	( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT)|
	( 0 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT) ;
	/* GPMC_AD4 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(4)) =
	( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT)|
	( 0 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT) ;
	/* GPMC_AD5 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(5)) =
	( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT)|
	( 0 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT) ;
	/* GPMC_AD6 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(6)) =
	( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT) ;
	/* GPMC_AD7 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(7)) =
	( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT) ;
	/* GPMC_AD8 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(8)) =
	( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE_SHIFT) ;
	/* GPMC_AD9 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(9)) =
	( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE_SHIFT) ;
	/* GPMC_AD10 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(10)) =
	( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE_SHIFT) ;
	/* GPMC_AD11 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(11)) =
	( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE_SHIFT) ;
	/* GPMC_AD12 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(12)) =
	( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE_SHIFT) ;
	/* GPMC_AD13 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(13)) =
	( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE_SHIFT) ;
	/* GPMC_AD14 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(14)) =
	( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE_SHIFT) ;
	/* GPMC_AD15 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_AD(15)) =
	( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL_SHIFT) |
	( 1 << CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE_SHIFT) ;

//	/* GPMC_WAIT0 */
//	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WAIT0) =
//	( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT) |
//	( 0 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT) |
//	( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT)|
//	( 1 << CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT);

//	/* GPMC_WPN */
//	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WPN) =
//	( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT) |
//	( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT) |
//	( 1 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT) |
//	( 0 << CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT);

	/* GPMC_CS1 */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_CSN(1)) =
	( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT)|
	( 1 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT)|
	( 0 << CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT);

	/* GPMC_ALE */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_ADVN_ALE) =
	( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT ) |
	( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT )  |
	( 1 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT);

//	/* GPMC_BE0N_CLE */
//	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_BE0N_CLE) =
//	( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT ) |
//	( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT )  |
//	( 1 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT) |
//	( 0 << CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT);

	/* GPMC_OEN_REN */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_OEN_REN) =
	( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT)  |
	( 1 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT);

	/* GPMC_WEN */
	HWREG(SOC_CONTROL_REGS + CONTROL_CONF_GPMC_WEN) =
	( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT)  |
	( 1 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT) |
	( 0 << CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT);
	 status = TRUE;

    return status;
}

int	 GPMCFPGAInit(void)
{
    unsigned int conf;
    unsigned int baseAddr;
    unsigned int cs;
    volatile unsigned int timeOut;

    conf = 0;
    timeOut =0xFFFF;
    baseAddr = SOC_GPMC_0_REGS;
    cs=1;

    /* GPMC Module configuration */
    GPMCModuleSoftReset(baseAddr);
    while((GPMCModuleResetStatusGet(baseAddr) != 1) && (timeOut != 0))
    {
        timeOut--;
    }
    if(timeOut == 0)
    {
        return (FALSE);
    }

    GPMCIdleModeSelect(baseAddr, GPMC_IDLEMODE_NOIDLE);

    /* Disable all interrupts */
    GPMCIntDisable(baseAddr, GPMC_FIFOEVENT_INT);
    GPMCIntDisable(baseAddr, GPMC_TERMINALCOUNT_INT);
    GPMCIntDisable(baseAddr, GPMC_WAIT0EDGEDETECTION_INT);
    GPMCIntDisable(baseAddr, GPMC_WAIT1EDGEDETECTION_INT);

    /* Timeout control disable */
    GPMCTimeOutFeatureConfig(baseAddr, GPMC_TIMEOUTFEATURE_DISABLE);
    GPMCCSConfig(baseAddr, cs, GPMC_CS_DISABLE);

    /* Set the wait pin polarity */
    GPMCWaitPinSelect(baseAddr, cs, GPMC_WAIT_PIN1);
    GPMCWaitPinPolaritySelect(baseAddr, GPMC_WAIT_PIN1, GPMC_WAIT_PIN_POLARITY_HIGH);
    GPMCWriteProtectPinLevelCtrl(baseAddr, GPMC_WP_PIN_LEVEL_HIGH);
    GPMCLimitedAddrDevSupportConfig(baseAddr, GPMC_LIMITEDADDRESS_SUPPORT_ENABLE);
    GPMCWaitPinMonitoringConfig(baseAddr, cs, GPMC_MODE_READ, GPMC_WAITMONITORING_DISABLE);
    GPMCWaitPinMonitoringConfig(baseAddr, cs, GPMC_MODE_WRITE, GPMC_WAITMONITORING_DISABLE);

    GPMCTimeParaGranularitySelect(baseAddr, cs, GPMC_TIMEPARAGRANULARITY_X1);
    GPMCDevTypeSelect(baseAddr, cs, GPMC_DEVICETYPE_NORLIKE);
    GPMCDevSizeSelect(baseAddr, cs, GPMC_DEVICESIZE_16BITS);
    GPMCAddrDataMuxProtocolSelect(baseAddr, cs, GPMC_MUXADDDATA_ADMUX);

    GPMCWriteTypeSelect(baseAddr, cs, GPMC_WRITETYPE_ASYNC);
    GPMCReadTypeSelect(baseAddr, cs, GPMC_READTYPE_ASYNC);
    GPMCAccessTypeSelect(baseAddr, cs, GPMC_MODE_WRITE, GPMC_ACCESSTYPE_SINGLE);
    GPMCAccessTypeSelect(baseAddr, cs, GPMC_MODE_READ, GPMC_ACCESSTYPE_SINGLE);

    GPMCBaseAddrSet(baseAddr, cs, (FPGA_BASE_ADDRESS) >> 24);
    GPMCMaskAddrSet(baseAddr, cs, (GPMC_CS_SIZE_16MB));

    conf = GPMC_CS_TIMING_CONFIG(7,								//CSWrOffTime
                                 7,								//CSRdOffTime
                                 FALSE,							//CSExtDelayFlag
                                 0);							//CSOnTime
    GPMCCSTimingConfig(baseAddr, cs, conf);

    conf = GPMC_ADV_TIMING_CONFIG(0,							//ADVAADMuxWrOffTime
                                  0,							//ADVAADMuxRdOffTime
                                  1,							//ADVWrOffTime
                                  1,							//ADVRdOffTime
                                  FALSE,						//ADVExtDelayFlag
                                  0,							//ADVAADMuxOnTime
                                  0);							//ADVOnTime
    GPMCADVTimingConfig(baseAddr, cs, conf);

    conf = GPMC_WE_OE_TIMING_CONFIG(6,							//WEOffTime
                                    FALSE,						//WEExtDelayFlag
                                    2,							//WEOnTime
                                    0,							//OEAADMuxOffTime
                                    6,							//OEOffTime
                                    FALSE,						//OEExtDelayFlag
                                    0,							//OEAADMuxOnTime
                                    2);							//OEOnTime
    GPMCWEAndOETimingConfig(baseAddr, cs, conf);

    conf = GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(
                                   8,							//rdCycleTime
                                   8,							//wrCycleTime
                                   6,							//rdAccessTime
                                   0);							//pageBurstAccessTime
    GPMCRdAccessAndCycleTimeTimingConfig(baseAddr, cs, conf);

    conf = GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(
                                  1,							//cycle2CycleDelay
                                  TRUE,							//cycle2CycleDelaySameCSCfg
                                  TRUE,							//cycle2CycleDelayDiffCSCfg
                                  0);							//nandTimingInfo->busTAtime
    GPMCycle2CycleAndTurnArndTimeTimingConfig(baseAddr, cs, conf);

    GPMCWrAccessAndWrDataOnADMUXBusTimingConfig(baseAddr, cs,
                                                8,				//wrAccessTime
                                                8);				//wrDataOnADMux
    GPMCCSConfig(baseAddr, cs, GPMC_CS_ENABLE);

    return(TRUE);
}

0 Biser Gatchev-XID over 12 years ago in reply to eugenio

TI__Guru**** 393215 points

Eugenio,

Can you dump the values that you write into the padconfig and GPMC config registers and post them?

0 eugenio over 12 years ago in reply to Biser Gatchev-XID

Expert 1505 points

Sure!

In attached the spreadsheet you can see:

"GPMC" sheet containg GPMC config registers dump; in yellow are the registers values touched by init code;
"PAD" sheet with I/O pad config values

1524.GPMC register dump.xls

NOTE: when dumping GPMC register starting at address 0x50000000 JTAG error console shows an error; here you can find a screenshot:

0 Biser Gatchev-XID over 12 years ago in reply to eugenio

TI__Guru**** 393215 points

Hi Eugenio,

The main problem as I see it, is that you have mapped wrong CS base address value into GPMC_CONFIG7_1 (address 0x500000A8), bits [5...0]. Your base address is 0x20000000, which falls outside the 512MB GPMC memory region. See AM335X TRM, section 7.1.5.17 for GPMC_CONFIG7_i values and Table 2-1, first row for GPMC memory region.

0 eugenio over 12 years ago in reply to Biser Gatchev-XID

Expert 1505 points

Thank you!

I was a bit confused about TRM. It says that CONFIG7_i [5..0] are A[28..24] address bits. So I understand that to set 0x0100_000 as base address I need to configure CONFIG7_i register this way: 0x0000_0F41, but this is NOT CORRECT.

This is the recipe I to get it working:

#define FPGA_BASE_ADDRESS (0x00800000)

GPMCBaseAddrSet(baseAddr, cs, (FPGA_BASE_ADDRESS) >> 23);

0 Biser Gatchev-XID over 12 years ago in reply to eugenio

TI__Guru**** 393215 points

Did you get it working then? I didn't understand from your post.

0 eugenio over 12 years ago in reply to Biser Gatchev-XID

Expert 1505 points

No. CPU/JTAG now seems to work properly, but I can't see any activity on \CS1, \RD, \WR signals...

So, I try to summarize: I want to read/write to an external device (FPGA), connected to AD[0..15] multiplexed data bus. Only 16bit read/write access are allowed, no burst operation, no wait signal is needed. FPGA is connected to \CS1. I don't care base address value, and I need 65Kword address space (16bit wide address).

I can't understand why you say that CONFIG7_1=0x0000_0F50 set the base address at 0x2000_0000. TRM says it's 0x1000_0000 (but limit value 0x3F points to 0x3FFF_FFFF, well above GPMC address space)...

Hope next life I'll be a smarter guy...

0 Biser Gatchev-XID over 12 years ago in reply to eugenio

TI__Guru**** 393215 points

Hi Eugenio,

Guess I haven't been too smart either. This is what I found in the AM335X TRM Rev.G, on the bottom of page 256:

- Asynchronous page mode is not supported for multiplexed address and data devices.

I can only hope that this doesn't cause a major setback on your project.

0 eugenio over 12 years ago in reply to Biser Gatchev-XID

Expert 1505 points

This is my conclusion (by now):

after GPMC reset, register CONFIG6_i becomes 0x8F070000; TRM states that CONFIG6_i[31] should be 0, altough reserved.
any subsequent call to GPMCycle2CycleAndTurnArndTimeTimingConfig() and GPMCWrAccessAndWrDataOnADMUXBusTimingConfig() doesn't touch bits 28..31 of CONFIG6_i, because these functions set new register value through the result of an OR operation (old value OR new value) --> any '1' bit can't be changed to zero, even if needed!)
If CONFIG6_i[19:16]=0xF then GPMC data access (write or read) cause CPU/JTAG stop working.

So, to get it work properly:

write 0x0000_0000 to CONFIG6_i register before any configuration
avoid that CONFIG6_i[19:16]=0xF.

Next step is verify data integrity and understand the base address configuration values

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AM3359 GPMC issue