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DM368 Interrupt Vector problem

Hennessy
Intellectual 920 points

Hi Engineers

 

My system specification is like below

CPU : DM368-432MHz, DDR-360MHz

OS : Non OS

Flash Memory :   Both NAND and NOR

CCS : V5.x

We can select NAND/NOR boot using option register -- BTSEL[2:0], AECFG[2:0], CE0, CE1

========

With these environment, i did like below

1. USE NAND Flash Boot Mode  : OK

    - BTSEL[2:0] = 000, AECFG[2:0] = 0xx

    - NAND - CE0, NOR - CE1

    - UBL, UBOOT, Application Code reside in NAND

2. USE NOR Flash Boot mode : NG 

    - BTSEL[2:0] = 001, AECFG[2:0] = 101

    - NOR(CE0), NAND(CE1)

    - UBL, UBOOT, Application code reside in NOR

    --> In this case, if i disable all interrupt then : OK 

    --> if i enable even only 1 interrupt, IRQ jump to 0x02000018 instead 0x00000018, i made VINTH signal to "L" using CP15 command at boot.asm

       

    Below is my CCS dump after breakpoint at 0x02000018 using CCS V5.x

 

    Same Board and software, different Boot mode ??

    Thanks in advance

 

  • 0
    Intellectual 920 points

     

    For more information,

     

    I made an breakpoint at 0x02000018 and start the system. 

     

    After jumping to 0x02000018, i did 2 things like below

        1. Compulsorily edit the PC to 0x80008040 which is the entry point of Application Code

            --> Do code initial and after enabling the interrupt,  again jump to 0x02000018

        2. Compulsorily edit the PC to 0x00000018 which has right IRQ vector. 

            --> In this case, the system can't read the ARM internal memory like below CCS dump

     

    Thanks for reading.

    Hennessy

     

     

     

     

     

  • 0 in reply to Hennessy
    Guru 31670 points

    Hennessy,

    Couple of questions:

    1. Did you enable MMU?

    2. Have you enabled I and D caches?

  • 0 in reply to Renjith Thomas
    Intellectual 920 points

    Dear Renjith

     

    Appreciate for your response.

    MMU is Disabled and I/D Caches are Enabled.

     

    I also tested I/D caches disabled but the result is not changed.

     

    Regards

    Hennessy

     

  • 0 in reply to Hennessy
    Guru 31670 points

    Hennessy,

    If you read the ARM subsystem document, at section 11.1 in the boot mode overview the following paragraph 

    "After reset (POR, warm reset, or max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[2:0] = 001, indicating AEMIF (OneNand/NOR) flash boot. See Section 10 for information on the boot selection pins."

    I think this means that in NOR/OneNAND bootmode, it will not even jump to BootROM, which will might result in not initializing/powering up the IRAM memories. I hope this explanation is satisfactory.

  • 0 in reply to Renjith Thomas
    Intellectual 920 points

    Renjith

     

    The problem was solved when i re-enabled the I/D TCM even it already enabled .

    Thank you for your kind help.

     

    Best Regards

    Hennessy