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c6670 Accumulator generates only one interrupt

Hi,

Please find below the prototype scenario and problem -

Prototype scenario : Interrupt based Network -> Core communication

                                     Packet accelerator posts packets to QMSS Queue (Configured as High priority Q).

                                     Accumulator is configured to monitor this Queue with below key parameters -

                                     AccumulatorCfg.maxPageEntries             =     1+1;
                                     AccumulatorCfg.timerLoadCount              =     0;
                                     AccumulatorCfg.interruptPacingMode      =     Qmss_AccPacingMode_LAST_INTERRUPT;
                                     AccumulatorCfg.listEntrySize                      =     Qmss_AccEntrySize_REG_D;
                                     AccumulatorCfg.listCountMode                  =     Qmss_AccCountMode_ENTRY_COUNT;
                                     AccumulatorCfg.multiQueueMode             =     Qmss_AccQueueMode_SINGLE_QUEUE;

Problem                   :  Irrespective of number of input packets posted into queue, only one interrupt is generated from accumulator.

                                      I have taken care of Acknowledge and Clearing of End Of Interrupt register in Interrupt Service Routine as given below -

                                      Void     Rx_ISR (Void)

                                       {

                                           ............... process interrupt....................

                                           /*Acknowledge interrupt and clear EOI register*/

                                           Qmss_ackInterrupt (channel, 1);

                                           Qmss_setEoiVector (Qmss_IntdInterruptType_HIGH, channel);

                                       }

                        In addition, return value of Qmss_ackInterrupt() and Qmss_setEoiVector() is observed as QMSS_ACC_IDLE (Decimal 0).

                        whereas according to QMSS LLD spec, the mentioned APIs shall return QMSS_ACC_SOK (Decimal 1) as success status.

                        what is meant by QMSS_ACC_IDLE here and what might be the reason for getting this return value ?

Below is test observation for mentioned configurations -

S. No.

Accumulator Configuration used

Outcome

Remark

1

No Of Input Packet                        =  3

Accumulator buffer threshold  =  1

Timer Load count                           =  0

Int Pacing mode : Same behavior for all possible modes

(i.e. NONE and 3 TIMER modes)

1 interrupt

1 packet received

 

2

No Of Input Packet                        =  3

Accumulator buffer threshold  =  3

Timer Load count                           =  40000

Int Pacing mode : Same behavior for all possible modes

(i.e. NONE and 3 TIMER modes)

1 interrupt

3 packets received

If value of Timer Load Count is 0, Only one packet is received while using Timer Mode as Interrupt pacing.

3

No Of Input Packet                        =  3

Accumulator buffer threshold  =  10

Timer Load count                           =  40000

Int Pacing mode                             :  TIMER modes

1 interrupt

3 packets received

 

4

No Of Input Packet                        =  3

Accumulator buffer threshold  =  10

Timer Load count                           =  40000

Int Pacing mode                             :   NONE (Threshold                           based)

NO Interrupt

 

5

No Of Input Packet                        =  8

Accumulator buffer threshold  =  3

Timer Load count                           =  40000

Int Pacing mode : Same behavior for all possible modes

(i.e. NONE and 3 TIMER modes)

1 interrupt

3 packets received

 

Please help me in understanding why Accumulator is not generating any further interrupts after the fist one.

  • HI Jitendra, 

    The QMSS_ACC_IDLE means as the names suggests, that the accumulator is idle for the QMSS. This means even though interrupts are being produced (since you're sending packets) the accumulator isn't responding and is unable to process them. For example, the accumulator send the interrupt to the CPU, and waits for the handshake. 

    Could you give out some more details? The fact that not all of the packets are being sent suggests that your setup is not correct for the channel in the first place. What are you two start and destination points? I'm assuming It's from one tx queue to a rx queue. I suspect it's really just your setup and configuration. 


    Make sure you're doing the EOI clear correctly. Because if the ISR is slow, then packets might arrive before they set EOI and of course the accumulator will set the interrupt bit, but it will be missed by the core because it does not get interrupted again until the EOI is set and the interrupts are 'turned on" again.