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REFCLK on BOC

Delared Delared
Expert 1945 points

Hi,

Object: Communication PCIe between 2 EVM  [TMDXEVM6678L]

In the BOC’s User Guide, it is mentioned that “The BoC has the capability of supplying a common REFCLK both EVM’s. This common REFCLK is generated on the BoC and sourced from a dedicated differential oscillator “

SO, In my case, What REFCLK should I use??

1-      Each DSP with its own REFCLK.

2-      Common REFCLK generated on the BoC

And the JP10 REFCLK Enable Header should be made Enabled or Disabled??

Thank’s

  • 0
    TI__Genius 12065 points

    If you are talking about the PCIe REFCLK, please take a look at the section XVI in BOC user guide, JP3 is the header to enable/disable the PCIe common reference clock. 

    By default the shunt is installed on JP3 and the PCIEREFCLK output is disabled. And by default, the EVM is using its local clock generator for the PCIe reference clock.

    So you are using its own  PCIe refclk on each EVM by default.

    If you need to use the common refclk for both EVMs provided by BOC, you need to remove the shunt from JP3, and also need to program "ICS557_SEL" bit to 1 in each FPGA on the EVM to select AMC reference clock as PCIe clock (refer to C6678 EVM TRM for details) in any boot mode, other than PCIe boot mode.

    If you are using PCIe boot mode, you need to use SW5.3 to select the ICS557_SEL pin (refer to C6678 EVM TRM for details).