Issues with MCASP on Linux/DM8168

Hi Shawn,

Did you tried num_serializer to 1 ? (Although I tried with no effect)

I'm working on DM8168 McASP with AIC23, base on DVRRDK3.50.00.05.

Problems were found at capture and playback:

1. playback program halt at snd_pcm_mmap_writei after several writes. No signal at AXR pin but also found "ALSA sound/core/pcm_lib.c:1765: playback write error (DMA or IRQ trouble?)" in dmesg.

2. arecord has no input.

Hardware measured AHCLK and AFSR /AFSX are normal.

DAVINCI_MCASP_TXSTAT_REG have error when first run, then no errors.

DAVINCI_MCASP_TXCLKCHK_REG counting ok

Any idea? Thanks.

Mike

 Tried setting num_serializer to 1, also to no effect.  

 I also just realized that each McASP on the 8168 has only 6 serializers, despite there being 16 control registers, so I guess not being able to set serializers 6-15 is a non-issue, but I changed the array size to 6, still to no positive effect.

 I'm still looking into this issue.  Thank you for any help.

I've made a bit of progress here. The GBLCTRL register is not being set.  According to section 14.3.8 of the technical manual, this is likely because there's no active clock to latch it.  I have however not been succesful in enabling the internal clock source - they seem to be getting reset to the external source before the attempted set of GBLCTL.

Also I should mention, the function in davinci-mcasp.c:

static inline void mcasp_set_ctl_reg(void __iomem *regs, u32 val)
{
      int i = 0;

      mcasp_set_bits(regs, val);

      /* programming GBLCTL needs to read back from GBLCTL and verfiy */
      /* loop count is to avoid the lock-up */
      for (i = 0; i < 1000; i++) {
            if ((mcasp_get_reg(regs) & val) == val)
                  break;
      }

      if (i == 1000 && ((mcasp_get_reg(regs) & val) != val))
            printk(KERN_ERR "GBLCTL write error\n");
}

appears either not exaclty right, or appears to be used improperly in the driver I'm looking at.  The driver code (found in linux-04.04.00.01) calls it with the alias register GBLCTLR, which does not appear to be subject to the same latching issue as GBLCTL, negating any usefulness of verifying the write..  i.e. it's verifying the write to the alias register and not to the actual register.

Edit: got the GBLCTL bits so set by setting/clearing the clock source bits around the GBLCTL sets.  Still getting read errors.

Which clock are you using ? ACLK or AHCLK ?

if you use AHCLK, you'll need to enable it before setting GBLCTL using mcasp_ahclkx_enable.

I could set it but still getting error

I'm not sure I understand what you mean by which clock am I using?  I was under the impression that both clocks are needed.  Both are externally generated, with AHCLKR always being on.

I think I'm to the point where I'm pretty happy with what I'm seeing in the register dumps of the MCASP1 region of memory, but I'm still getting read errors.  I don't really know where to look next.

I am working on DM8148 and use McAsp3 to connect AIC3106. I made it running. 

I want to share for everybody.

in the board-ti8148ipnc.c

//panda
static u8 ti8148_iis_serializer_direction_1[] = {
	TX_MODE,	RX_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,	INACTIVE_MODE,
};
static struct snd_platform_data ti8148_evm_snd_data[] = {
		{
			.tx_dma_offset	= 0x46800000,
			.rx_dma_offset	= 0x46800000,
			.op_mode	= DAVINCI_MCASP_IIS_MODE,
			.num_serializer = ARRAY_SIZE(ti8148_iis_serializer_direction),
			.tdm_slots	= 2,
			.serial_dir	= ti8148_iis_serializer_direction,
			.asp_chan_q	= EVENTQ_2,
			.version	= MCASP_VERSION_2,
			.txnumevt	= 64,
			.rxnumevt	= 64,
		},
		{
			.tx_dma_offset	= 0x4A1A5000,
			.rx_dma_offset	= 0x4A1A5000,
			.op_mode	= DAVINCI_MCASP_IIS_MODE,
			.num_serializer = ARRAY_SIZE(ti8148_iis_serializer_direction_1),
			.tdm_slots	= 2,
			.serial_dir	= ti8148_iis_serializer_direction_1,
			.asp_chan_q	= EVENTQ_2,//??
			.version	= MCASP_VERSION_2,
			.txnumevt	= 1,//?
			.rxnumevt	= 1,//?
		}

};

also add a register line in function ti8148_ipnc_init

ti81xx_register_mcasp(3, &ti8148_evm_snd_data[1]);

in the devices.c

static struct resource ti81xx_mcasp3_resource[] = {
	{
		.name = "mcasp",
		.start = TI81XX_ASP3_BASE,
		.end = TI81XX_ASP3_BASE + (SZ_1K * 12) - 1,
		.flags = IORESOURCE_MEM,
	},
	/* TX event */
	{
		.start = TI81XX_DMA_MCASP3_AXEVT,
		.end = TI81XX_DMA_MCASP3_AXEVT,
		.flags = IORESOURCE_DMA,
	},
	/* RX event */
	{
		.start = TI81XX_DMA_MCASP3_AREVT,
		.end = TI81XX_DMA_MCASP3_AREVT,
		.flags = IORESOURCE_DMA,
	},
};
static struct platform_device ti81xx_mcasp3_device = {
	.name = "davinci-mcasp",
};

with some defination in the asp.h

//panda
/* EDMA channels of ti81xx McASP3 */
#define TI81XX_DMA_MCASP3_AXEVT 56
#define TI81XX_DMA_MCASP3_AREVT 57
//~panda

//panda
#define TI81XX_ASP3_BASE 0x4A1A2000
//~panda

modify ti81xx_register_mcasp function in devices.c like that:

void __init ti81xx_register_mcasp(int id, struct snd_platform_data *pdata)
{
	if (id==2)
	{
	if (machine_is_ti8168evm() || machine_is_ti8148evm() || machine_is_ti811xevm() || machine_is_ti8148ipnc()) {
		ti81xx_mcasp_device.id = 2;
		ti81xx_mcasp_device.resource = ti81xx_mcasp_resource;
		ti81xx_mcasp_device.num_resources = ARRAY_SIZE(ti81xx_mcasp_resource);
	} else if (machine_is_dm385evm() || machine_is_dm385ipnc()) {
		ti81xx_mcasp_device.id = 1;
		ti81xx_mcasp_device.resource = dm385_mcasp_resource;
		ti81xx_mcasp_device.num_resources = ARRAY_SIZE(dm385_mcasp_resource);
	} else {
		pr_err("%s: platform not supported\n", __func__);
		return;
	}

	/* TI811x AIC_MCLK is connected to SoC pin MCA2_AHCLKX */
	//omap_mux_init_signal("xref_clk2.mcasp2_ahclkx", 0);
	ti81xx_mcasp_device.dev.platform_data = pdata;
	platform_device_register(&ti81xx_mcasp_device);
}
	if (id==3)
	{
		if (machine_is_ti8168evm() || machine_is_ti8148evm() || machine_is_ti811xevm() || machine_is_ti8148ipnc()) {
			ti81xx_mcasp3_device.id = 3;
			ti81xx_mcasp3_device.resource = ti81xx_mcasp3_resource;
			ti81xx_mcasp3_device.num_resources = ARRAY_SIZE(ti81xx_mcasp3_resource);
		} else if (machine_is_dm385evm() || machine_is_dm385ipnc()) {
			ti81xx_mcasp3_device.id = 3;
			ti81xx_mcasp3_device.resource = dm385_mcasp_resource;
			ti81xx_mcasp3_device.num_resources = ARRAY_SIZE(dm385_mcasp_resource);
		} else {
			pr_err("%s: platform not supported\n", __func__);
			return;
		}

		/* TI811x AIC_MCLK is connected to SoC pin MCA2_AHCLKX */
		//omap_mux_init_signal("xref_clk2.mcasp2_ahclkx", 0);
		ti81xx_mcasp3_device.dev.platform_data = pdata;
		platform_device_register(&ti81xx_mcasp3_device);
	}
}

finally , due to dma for mcasp 345 work on dsp so We have modify on devices.c dma slot and dma channel rsv :

static const s16 ti814x_dma_rsv_chans[][2] = {
/* (offset, number) */
{0, 2},
{14, 2},
{26, 6},
{48, 4},
{58, 6},//panda {56,8}
{-1, -1}
};

static const s16 ti814x_dma_rsv_slots[][2] = {
/* (offset, number) */
{0, 2},
{14, 2},
{26, 6},
{48, 4},
{58, 6},//panda {56,8}
{64, 127},
{-1, -1}
};

(for this one, please read http://processors.wiki.ti.com/index.php/TI81XX_EDMA_Driver_User_Guide )

finally, mcasp3 work on the A8.

i am amateur, i just want share what i done, forgive me if i have mistake.

thank you

(I spent alot of time to fix bug "davinci_pcm: Failed to get dma channels" . So i want to help who have same situation)