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UDDVR (RDK03.50.00.05) XGA display not clarify in the playback mode

kisung cho
Expert 1460 points



Hi. 

i checked this issue(playback us not clarify) for a long time. 

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/237862.aspx?pi239031349=2

when i change playback mode , playback displayed video data is not clairfied , it's seen blured.

it is seen in the mode of MULTICH_LAYOUT_MODE_16CH . it's not seen MULTICH_LAYOUT_MODE_13CH and MULTICH_LAYOUT_MODE_4CH

thus i changed like belows. currently it's seen clarified. why it is not seen blured when i set force upscaling?

is there any check point scaling coeffs?

/dvr_rdk/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c

Int32 SwMsLink_drvSetScCoeffs(SwMsLink_Obj * pObj, FVID2_Handle fvidHandle,
                UInt32 curCoeffId_v, UInt32 curCoeffId_h, Bool isDei)
{
    Int32 retVal = FVID2_SOK;
    Vps_ScCoeffParams coeffPrms;
    static char *scCoeffName[VPS_SC_SET_MAX] =
    {
        "3/16",
        "4/16",
        "5/16",
        "6/16",
        "7/16",
        "8/16",
        "9/16",
        "10/16",
        "11/16",
        "12/16",
        "13/16",
        "14/16",
        "15/16",
        "UPSCALE",
        "1/1",
    };

    //if(curCoeffId_h>=VPS_SC_SET_MAX) -- FORCE TO UPSCALE
        curCoeffId_h = VPS_SC_US_SET;

    //if(curCoeffId_v>=VPS_SC_SET_MAX) -- FORCE TO UPSCALE
        curCoeffId_v = VPS_SC_US_SET;

 }

Best Regards.

  • 0
    Expert 1460 points

    In addition. i checked the log with below func.

    when i checked Co-effs value live and pb, Co-effs value is same. i don't know why this issue occured. 

    what do you think about that?


    LIVEMODE

    LAYOUT_16CH(OK)

            [m3vpss ] after 522770: SWMS0 : Loading Vertical Co-effs (6/16)x ...
            [m3vpss ] after 522771: SWMS0 : Loading Horizontal Co-effs (5/16)x ..


    PLAYBACKMODE

    LAYOUT_4CH(OK)

            [m3vpss ] after 356816: SWMS0 : Loading Vertical Co-effs (12/16)x ...
            [m3vpss ] after 356816: SWMS0 : Loading Horizontal Co-effs (11/16)x ...

    LAYOUT_13CH (OK)

            [m3vpss ] after 251189: SWMS0 : Loading Vertical Co-effs (12/16)x ...
            [m3vpss ] after 251190: SWMS0 : Loading Horizontal Co-effs (11/16)x

    LAYOUT_16CH (FAIL)

            [m3vpss ] after 406125: SWMS0 : Loading Vertical Co-effs (6/16)x ...  
            [m3vpss ] after 406126: SWMS0 : Loading Horizontal Co-effs (5/16)x ...


    it's my full log

    5342.201302202219.txt

    Int32 SwMsLink_drvSetScCoeffs(...)

    { ...

    Vps_rprintf("before %d: %s : Loading Vertical Co-effs (%s)x ... \n",
    Utils_getCurTimeInMsec(), pObj->name, scCoeffName[curCoeffId_v]
    );
    Vps_rprintf("before %d: %s : Loading Horizontal Co-effs (%s)x ... \n",
    Utils_getCurTimeInMsec(), pObj->name, scCoeffName[curCoeffId_h]
    );


    if(curCoeffId_h>=VPS_SC_SET_MAX) // kisung cho
    curCoeffId_h = VPS_SC_US_SET;

    if(curCoeffId_v>=VPS_SC_SET_MAX) // kisung cho
    curCoeffId_v = VPS_SC_US_SET;


    Vps_rprintf("after %d: %s : Loading Vertical Co-effs (%s)x ... \n",
    Utils_getCurTimeInMsec(), pObj->name, scCoeffName[curCoeffId_v]
    );
    Vps_rprintf("after %d: %s : Loading Horizontal Co-effs (%s)x ... \n",
    Utils_getCurTimeInMsec(), pObj->name, scCoeffName[curCoeffId_h]
    );

    }

  • 0 in reply to kisung cho
    TI__Guru 59700 points

    Can you apply attached patch on HDVPSS driver from Brijesh and check if it improves the issue. The firmware has to be rebuilt after applying patch.

    Do:

    make clean

    rm -rf build

    make dvr_rdk

    Fullscreen 6622.0001-ScHal-Below-changes-are-done.patch.txt Download 
    From 2e9127780a8d9cd51bb92c67954272a5c0b09ed1 Mon Sep 17 00:00:00 2001
From: Brijesh Jadav <Brijesh.Jadav@ti.com>
Date: Fri, 21 Dec 2012 14:31:50 +0530
Subject: [PATCH] ScHal: Below changes are done

When AUTO is used for horizontal scaling, scalar hal is modified
to use polyphase filter for 1/4x to 1x scaling factor, 2x decimation is
used for scaling factor 1/8x to 1/4x and 4x decimation is used for
scaling factor 1/16x to 1/8x.
---
 packages/ti/psp/vps/hal/src/vpshal_sc.c |  338 +++++++++++++++++++++++--------
 1 file changed, 251 insertions(+), 87 deletions(-)

diff --git a/packages/ti/psp/vps/hal/src/vpshal_sc.c b/packages/ti/psp/vps/hal/src/vpshal_sc.c
index 745462f..412e954 100755
--- a/packages/ti/psp/vps/hal/src/vpshal_sc.c
+++ b/packages/ti/psp/vps/hal/src/vpshal_sc.c
@@ -652,6 +652,7 @@ Int VpsHal_scSetConfig(VpsHal_Handle handle,
     UInt32 value, confFactor;
     Int ret = 0;
     Sc_ScalarInfo *scInfo = NULL;
+    UInt32 srcInnerWidth, tarInnerWidth;
 
     GT_assert( VpsHalTrace, (NULL != handle));
     GT_assert( VpsHalTrace, (NULL != config));
@@ -722,19 +723,77 @@ Int VpsHal_scSetConfig(VpsHal_Handle handle,
                      CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK |
                      CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK |
                      CSL_VPS_SC_H_CFG_SC0_CFG_HP_BYPASS_MASK));
-        switch(config->hsType)
+
+        if (VPS_SC_HST_AUTO == config->hsType)
         {
-            case VPS_SC_HST_AUTO:
-                value |= CSL_VPS_SC_H_CFG_SC0_CFG_AUTO_HS_MASK;
-                break;
-            case VPS_SC_HST_DCM_2X:
-                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK;
-                break;
-            case VPS_SC_HST_DCM_4X:
-                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK;
-                break;
-            case VPS_SC_HST_POLYPHASE:
-                break;
+            /* All scaling ratio are calculated based on the inner size of the
+             * source and the targer image */
+            if (TRUE == config->nonLinear)
+            {
+                /* For nonlinear scaling, source inner width is height and target
+                 * inner is calculated based on strip size */
+                srcInnerWidth = config->cropHeight;
+                tarInnerWidth = config->tarWidth - (config->stripSize << 1u);
+            }
+            else /* Linear horizontal Scaling */
+            {
+                /* For linear scaling, inner size is same width */
+                srcInnerWidth = config->cropWidth;
+                tarInnerWidth = config->tarWidth;
+            }
+
+            /* Use polyphase filter for upscaling and down scaling from 1x to 1/4x.
+             * Use 2x decimation from 1/4x to 1/8x and rest using polyphase.
+             * Use 4x decimation from 1/8x to 1/16x and rest using polyphase.
+             */
+            if (tarInnerWidth >= srcInnerWidth)
+            {
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
+            }
+            else
+            {
+                /* Down Scaling between 1/4 and 1 */
+                if (tarInnerWidth >= (srcInnerWidth >> 2u))
+                {
+                    /* Down Scaling without Decimation */
+                    value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+                    value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
+                }
+                /* Down Scaling between 1/8 and 1/4 */
+                else if (tarInnerWidth >= (srcInnerWidth >> 3u))
+                {
+                    /* 2x decimation */
+                    value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK;
+                    value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+                }
+                /* Down Scaling between 1/16 and 1/4 */
+                else if (tarInnerWidth >= (srcInnerWidth >> 4u))
+                {
+                    /* 4x decimation */
+                    value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK;
+                    value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
+                }
+                else
+                {
+                    /* Illegal Scaling factor. i.e. factor < 1/16 */
+                    ret = -1;
+                }
+            }
+        }
+        else
+        {
+            switch(config->hsType)
+            {
+                case VPS_SC_HST_DCM_2X:
+                    value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK;
+                    break;
+                case VPS_SC_HST_DCM_4X:
+                    value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK;
+                    break;
+                case VPS_SC_HST_POLYPHASE:
+                    break;
+            }
         }
 
         /* Enable nonlinear Algorighm */
@@ -863,6 +922,7 @@ Int VpsHal_scSetAdvConfig(VpsHal_Handle handle,
     UInt32          *scRegsOffset;
     UInt32          ravFactor, regRavFactor;
     UInt32          accInit, accIncr, offsetA, offsetB;
+    UInt32          srcInnerWidth, tarInnerWidth;
 
     GT_assert( VpsHalTrace, (NULL != handle));
     GT_assert( VpsHalTrace, (NULL != config));
@@ -890,19 +950,77 @@ Int VpsHal_scSetAdvConfig(VpsHal_Handle handle,
                  CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK |
                  CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK |
                  CSL_VPS_SC_H_CFG_SC0_CFG_HP_BYPASS_MASK));
-    switch(config->hsType)
+
+    if (VPS_SC_HST_AUTO == config->hsType)
     {
-        case VPS_SC_HST_AUTO:
-            value |= CSL_VPS_SC_H_CFG_SC0_CFG_AUTO_HS_MASK;
-            break;
-        case VPS_SC_HST_DCM_2X:
-            value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK;
-            break;
-        case VPS_SC_HST_DCM_4X:
-            value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK;
-            break;
-        case VPS_SC_HST_POLYPHASE:
-            break;
+        /* All scaling ratio are calculated based on the inner size of the
+         * source and the targer image */
+        if (TRUE == config->nonLinear)
+        {
+            /* For nonlinear scaling, source inner width is height and target
+             * inner is calculated based on strip size */
+            srcInnerWidth = config->cropHeight;
+            tarInnerWidth = config->tarWidth - (config->stripSize << 1u);
+        }
+        else /* Linear horizontal Scaling */
+        {
+            /* For linear scaling, inner size is same width */
+            srcInnerWidth = config->cropWidth;
+            tarInnerWidth = config->tarWidth;
+        }
+
+        /* Use polyphase filter for upscaling and down scaling from 1x to 1/4x.
+         * Use 2x decimation from 1/4x to 1/8x and rest using polyphase.
+         * Use 4x decimation from 1/8x to 1/16x and rest using polyphase.
+         */
+        if (tarInnerWidth >= srcInnerWidth)
+        {
+            value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+            value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
+        }
+        else
+        {
+            /* Down Scaling between 1/4 and 1 */
+            if (tarInnerWidth >= (srcInnerWidth >> 2u))
+            {
+                /* Down Scaling without Decimation */
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
+            }
+            /* Down Scaling between 1/8 and 1/4 */
+            else if (tarInnerWidth >= (srcInnerWidth >> 3u))
+            {
+                /* 2x decimation */
+                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK;
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+            }
+            /* Down Scaling between 1/16 and 1/4 */
+            else if (tarInnerWidth >= (srcInnerWidth >> 4u))
+            {
+                /* 4x decimation */
+                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK;
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
+            }
+            else
+            {
+                /* Illegal Scaling factor. i.e. factor < 1/16 */
+                ret = -1;
+            }
+        }
+    }
+    else
+    {
+        switch(config->hsType)
+        {
+            case VPS_SC_HST_DCM_2X:
+                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK;
+                break;
+            case VPS_SC_HST_DCM_4X:
+                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK;
+                break;
+            case VPS_SC_HST_POLYPHASE:
+                break;
+        }
     }
 
     /* Set the Vertical Scaling Algorithm */
@@ -1675,6 +1793,7 @@ Int VpsHal_scGetScFactorConfig(VpsHal_Handle handle,
     UInt32 *scRegsOffset;
     UInt32 ravFactor, regRavFactor;
     UInt32 accInit, accIncr, offsetA, offsetB;
+    Int32 coeffId_h, coeffId_v, numerator, denominator;
 
     GT_assert(VpsHalTrace, (NULL != handle));
     GT_assert(VpsHalTrace, (NULL != config));
@@ -1730,71 +1849,88 @@ Int VpsHal_scGetScFactorConfig(VpsHal_Handle handle,
         }
         else
         {
-            /* Down Scaling between 1/2 and 1 */
-            if (tarInnerWidth > (srcInnerWidth >> 1u))
+            /* Down Scaling between 1/4 and 1 */
+            if (tarInnerWidth >= (srcInnerWidth >> 2u))
             {
                 /* Down Scaling without Decimation */
                 scFactorConfig->hsType = VPS_SC_HST_POLYPHASE;
                 /* Polyphase filter used for scaling factor between 1/2 and 1 */
-                scFactorConfig->hScalingSet =
-                    ((tarInnerWidth << SC_COEFF_SCALE_SHIFT) / srcInnerWidth)
-                     - 4u;
+                srcInnerWidth = srcInnerWidth;
+                numerator = denominator = 16;
+                for(coeffId_h=VPS_SC_US_SET;coeffId_h>=VPS_SC_DS_SET_3_16; coeffId_h--)
+                {
+                    if( srcInnerWidth*numerator <= tarInnerWidth*denominator )
+                        break;
+                    numerator--;
+                }
+                scFactorConfig->hScalingSet = coeffId_h;
 
             }
-            /* Down Scaling exact 1/2 */
-            else if (tarInnerWidth == (srcInnerWidth >> 1u))
-            {
-                /* 2x decimation */
-                scFactorConfig->hsType = VPS_SC_HST_DCM_2X;
-                /* No usage of polyphase filter */
-                scFactorConfig->hScalingSet = VPS_SC_US_SET;
-            }
-            /* Down Scaling between 1/4 and 1/2 */
-            else if (tarInnerWidth > (srcInnerWidth >> 2u))
+            /* Down Scaling between 1/8 and 1/4 */
+            else if (tarInnerWidth >= (srcInnerWidth >> 3u))
             {
                 /* 2x decimation */
                 scFactorConfig->hsType = VPS_SC_HST_DCM_2X;
-                /* Polyphase filter used for scaling factor between 1/2 and 1 */
-                scFactorConfig->hScalingSet =
-                    (   (tarInnerWidth << SC_COEFF_SCALE_SHIFT)
-                     /  (srcInnerWidth >> 1u))
-                     - 4u;
+                srcInnerWidth = srcInnerWidth >> 1;
+                numerator = denominator = 16;
+                for(coeffId_h=VPS_SC_US_SET;coeffId_h>=VPS_SC_DS_SET_3_16; coeffId_h--)
+                {
+                    if( srcInnerWidth*numerator <= tarInnerWidth*denominator )
+                        break;
+                    numerator--;
+                }
+                scFactorConfig->hScalingSet = coeffId_h;
             }
-            /* Down Scaling exact 1/4 */
-            else if (tarInnerWidth == (srcInnerWidth >> 2u))
+            /* Down Scaling between 1/16 and 1/4 */
+            else if (tarInnerWidth >= (srcInnerWidth >> 4u))
             {
                 /* 4x decimation */
                 scFactorConfig->hsType = VPS_SC_HST_DCM_4X;
-                /* No usage of polyphase filter */
-                scFactorConfig->hScalingSet = VPS_SC_US_SET;
+                /* Polyphase filter used for scaling factor between 1/2 and 1 */
+
+                srcInnerWidth = srcInnerWidth >> 2;
+
+                numerator = denominator = 16;
+                for(coeffId_h=VPS_SC_US_SET;coeffId_h>=VPS_SC_DS_SET_3_16; coeffId_h--)
+                {
+                    if( srcInnerWidth*numerator <= tarInnerWidth*denominator )
+                        break;
+                    numerator--;
+                }
+                scFactorConfig->hScalingSet = coeffId_h;
             }
-            /* Down Scaling between 1/8 and 1/4 */
-            else if (tarInnerWidth >= (srcInnerWidth >> 3u))
+            else
             {
-                /* 4x decimation */
-                scFactorConfig->hsType = VPS_SC_HST_DCM_4X;
-                /* Polyphase filter used for scaling factor between 1/2 and 1 */
-                scFactorConfig->hScalingSet =
-                    (   (tarInnerWidth << SC_COEFF_SCALE_SHIFT)
-                     /  (srcInnerWidth >> 2u))
-                     - 4u;
+                /* Illegal Scaling factor. i.e. factor < 1/16 */
+                ret = -1;
             }
-            /* Down Scaling between 1/16 and 1/8 */
-            else if (tarInnerWidth >= (srcInnerWidth >> 4u))
+            config->hsType = scFactorConfig->hsType;
+            if (NULL == ovlyPtr)
             {
-                /* 4x decimation */
-                scFactorConfig->hsType = VPS_SC_HST_DCM_4X;
-                /* Polyphase filter used for scaling factor between 1/4 and 1/2
-                 */
-                scFactorConfig->hScalingSet =
-                    (   (tarInnerWidth << SC_COEFF_SCALE_SHIFT)
-                     /  (srcInnerWidth >> 3u))
-                     - 4u;
+                value = scInfo->regs->CFG_SC0;
             }
             else
             {
-                /* Illegal Scaling factor. i.e. factor < 1/16 */
-                ret = -1;
+                /* Get the Value from SC0 Register */
+                value = regr((UInt32 *) ovlyPtr +
+                        scInfo->virtRegOffset[SC_CONFIG_OVLY_CFG_SC0_IDX]);
+            }
+            /* Set auto HS to False always */
+            value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_AUTO_HS_MASK);
+            if (VPS_SC_HST_DCM_2X == config->hsType)
+            {
+                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK;
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+            }
+            else if (VPS_SC_HST_DCM_4X == config->hsType)
+            {
+                value |= CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK;
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
+            }
+            else if (VPS_SC_HST_POLYPHASE == config->hsType)
+            {
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_4X_MASK);
+                value &= ~(CSL_VPS_SC_H_CFG_SC0_CFG_DCM_2X_MASK);
             }
         }
 
@@ -1826,10 +1962,14 @@ Int VpsHal_scGetScFactorConfig(VpsHal_Handle handle,
                 if (config->tarHeight >= (config->cropHeight >> 2u))
                 {
                     scFactorConfig->vsType = VPS_SC_VST_POLYPHASE;
-                    scFactorConfig->vScalingSet =
-                        (   (config->tarHeight << SC_COEFF_SCALE_SHIFT)
-                         /  config->cropHeight);
-                    scFactorConfig->vScalingSet -= 3u;
+                    numerator = denominator = 16;
+                    for(coeffId_v=VPS_SC_US_SET;coeffId_v>=VPS_SC_DS_SET_3_16; coeffId_v--)
+                    {
+                        if( config->cropHeight*numerator <= config->tarHeight*denominator )
+                            break;
+                        numerator--;
+                    }
+                    scFactorConfig->vScalingSet = coeffId_v;
                 }
                 else
                 {
@@ -2473,23 +2613,47 @@ static inline UInt32 scCalHorzLinearAccInc(const VpsHal_ScConfig *config,
     GT_assert( VpsHalTrace, (NULL != config));
     GT_assert( VpsHalTrace, (NULL != shift));
 
-    if (config->tarWidth > config->cropWidth)
-    {
-        *shift = 0u;
-    }
-    else if (config->tarWidth <= (config->cropWidth >> 2u))
+    if (VPS_SC_HST_AUTO == config->hsType)
     {
-        *shift = 2u;
-    }
-    else if (config->tarWidth <= (config->cropWidth >> 1u))
-    {
-        *shift = 1u;
+        if (config->tarWidth > config->cropWidth)
+        {
+            *shift = 0u;
+        }
+        else if (config->tarWidth < (config->cropWidth >> 3u))
+        {
+            *shift = 2u;
+        }
+        else if (config->tarWidth < (config->cropWidth >> 2u))
+        {
+            *shift = 1u;
+        }
+        else /* No Decimation */
+        {
+            /* Since Decimation will not be used, there is no need to shift */
+            *shift = 0u;
+        }
     }
-    else /* No Decimation */
+    else
     {
-        /* Since Decimation will not be used, there is no need to shift */
-        *shift = 0u;
+        if (config->tarWidth > config->cropWidth)
+        {
+            *shift = 0u;
+        }
+        else if (config->tarWidth <= (config->cropWidth >> 2u))
+        {
+            *shift = 2u;
+        }
+        else if (config->tarWidth <= (config->cropWidth >> 1u))
+        {
+            *shift = 1u;
+        }
+        else /* No Decimation */
+        {
+            /* Since Decimation will not be used, there is no need to shift */
+            *shift = 0u;
+        }
     }
+
     if (TRUE == config->nonLinear)
     {
         srcInnerWidth = config->cropHeight;
@@ -2795,7 +2959,7 @@ static Int scCheckParams(VpsHal_Handle handle,
      * should not be used */
     if ((VPS_SC_HST_DCM_2X == config->hsType ||
         VPS_SC_HST_DCM_2X == config->hsType) &&
-        (1024 *  config->tarHeight > 512 * config->cropHeight))
+        (1024 *  config->tarWidth > 512 * config->cropWidth))
     {
         GT_0trace(VpsHalTrace, GT_ERR, "Wrong scaling ratio for decimation\n");
         ret = -1;
-- 
1.7.10.msysgit.1

  • 0 in reply to Badri Narayanan
    Expert 1460 points

    thank you Badri.

    it works good. 

  • 0 in reply to kisung cho
    TI__Guru 59700 points

    You had reported an other issue at : http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/p/241288/846487.aspx

    Do you see any improvement related to that issue after applying this patch.

  • 0 in reply to Badri Narayanan
    Expert 1460 points

    Hi . Thank you for your support.

    i checked another issue in the LAYOUT_1CH. i think if i tuning more little bit , it will be good.

     at the view of 45 degree's angle , sawtooth more noticeable.is there any point to imporve like RDK_03.00 images sawtooth?

    i attached my previous RDK image and patched current RDK image.

    1. DVRRDK_03.00.xx.00

    2. DVRRDK_03.50.00.05

    Best Regards. CHO

  • 0 in reply to kisung cho
    TI__Guru 59700 points

    Can you pls try with the attached patches. We are not seeing the issue in our setup so we are not sure if it will resolve the issue:

    Fullscreen 0216.0001-enabled-peaking-filter-by-default-for-all-scalars.patch.txt Download 
    From 955b18cc5d7f16e08b6750bcff9526d174159b0c Mon Sep 17 00:00:00 2001
From: shiju sivasankaran <s-sivasankaran1@ti.com>
Date: Thu, 28 Feb 2013 19:25:03 +0530
Subject: [PATCH] enabled peaking filter by default for all scalars

---
 mcfw/src_bios6/links_m3vpss/dei/deiLink_drv.c      |    2 +-
 .../links_m3vpss/display/displayLink_drv.c         |    2 +-
 .../src_bios6/links_m3vpss/mpSclr/mpSclrLink_drv.c |    1 +
 mcfw/src_bios6/links_m3vpss/sclr/sclrLink_drv.c    |    2 ++
 mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c    |    4 ++++
 5 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/mcfw/src_bios6/links_m3vpss/dei/deiLink_drv.c b/mcfw/src_bios6/links_m3vpss/dei/deiLink_drv.c
index 194c829..2736a7b 100755
--- a/mcfw/src_bios6/links_m3vpss/dei/deiLink_drv.c
+++ b/mcfw/src_bios6/links_m3vpss/dei/deiLink_drv.c
@@ -562,7 +562,7 @@ Int32 DeiLink_drvCreateChObj(DeiLink_Obj * pObj, UInt32 chId)
         pChObj->scCfg[outId].stripSize = 0;
         pChObj->scCfg[outId].vsType = VPS_SC_VST_POLYPHASE;
         pChObj->scCfg[outId].hsType = VPS_SC_HST_AUTO;
-
+        pChObj->scCfg[outId].enablePeaking = TRUE;
     }
 
     DeiLink_drvUpdateScCropPrm(pObj, chId);
diff --git a/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c b/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c
index 4b0cbbe..a60eb9b 100755
--- a/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c
+++ b/mcfw/src_bios6/links_m3vpss/display/displayLink_drv.c
@@ -862,7 +862,7 @@ Int32 DisplayLink_drvSetDeiDispPrms(DisplayLink_Obj *pObj, FVID2_Format *pFormat
     deiDispPrms->scCfg.stripSize = 0;
     deiDispPrms->scCfg.vsType = VPS_SC_VST_POLYPHASE;
     deiDispPrms->scCfg.hsType = VPS_SC_HST_AUTO;
-    deiDispPrms->scCfg.enablePeaking = FALSE;
+    deiDispPrms->scCfg.enablePeaking = TRUE;
     deiDispPrms->scCfg.enableEdgeDetect = FALSE;
 
     deiDispPrms->deiHqCfg = NULL;
diff --git a/mcfw/src_bios6/links_m3vpss/mpSclr/mpSclrLink_drv.c b/mcfw/src_bios6/links_m3vpss/mpSclr/mpSclrLink_drv.c
index 3ababae..6f97d2d 100755
--- a/mcfw/src_bios6/links_m3vpss/mpSclr/mpSclrLink_drv.c
+++ b/mcfw/src_bios6/links_m3vpss/mpSclr/mpSclrLink_drv.c
@@ -446,6 +446,7 @@ static Int32 mpSclrLinkDvrHndlCreate(MpSclrLink_Obj *pObj)
         pDrvChPrm->scCfg->stripSize = 0;
         pDrvChPrm->scCfg->vsType = VPS_SC_VST_POLYPHASE;
         pDrvChPrm->scCfg->hsType = VPS_SC_HST_POLYPHASE;
+        pDrvChPrm->scCfg->enablePeaking = TRUE;
 
         if(pObj->createArgs.enableLineSkip &&
            pChInfo->memType == VPS_VPDMA_MT_NONTILEDMEM)
diff --git a/mcfw/src_bios6/links_m3vpss/sclr/sclrLink_drv.c b/mcfw/src_bios6/links_m3vpss/sclr/sclrLink_drv.c
index 004a656..7861fe8 100755
--- a/mcfw/src_bios6/links_m3vpss/sclr/sclrLink_drv.c
+++ b/mcfw/src_bios6/links_m3vpss/sclr/sclrLink_drv.c
@@ -546,6 +546,7 @@ Int32 SclrLink_drvCreateChObj(SclrLink_Obj * pObj, UInt32 chId)
     pChObj->scCfg.stripSize = 0;
     pChObj->scCfg.vsType = VPS_SC_VST_POLYPHASE;
     pChObj->scCfg.hsType = VPS_SC_HST_AUTO;
+    pChObj->scCfg.enablePeaking = TRUE;
 
     return FVID2_SOK;
 }
@@ -636,6 +637,7 @@ Int32 SclrLink_drvCreateFvidObj(SclrLink_Obj * pObj)
         pDrvChPrm->scCfg->stripSize = 0;
         pDrvChPrm->scCfg->vsType = VPS_SC_VST_POLYPHASE;
         pDrvChPrm->scCfg->hsType = VPS_SC_HST_AUTO;
+        pDrvChPrm->scCfg->enablePeaking = TRUE;
 
         pDrvChPrm->srcCropCfg->cropStartX = 0;
         pDrvChPrm->srcCropCfg->cropStartY = 0;
diff --git a/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c b/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c
index e6cc412..756db04 100755
--- a/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c
+++ b/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c
@@ -2219,6 +2219,7 @@ Int32 SwMsLink_drvCreateDeiDrv(SwMsLink_Obj * pObj, SwMsLink_DrvObj *pDrvObj)
         pDrvChPrm->scCfg->stripSize = 0;
         pDrvChPrm->scCfg->vsType = VPS_SC_VST_POLYPHASE;
         pDrvChPrm->scCfg->hsType = VPS_SC_HST_AUTO;
+        pDrvChPrm->scCfg->enablePeaking = TRUE;
 
         pDrvChPrm->deiCropCfg->cropStartX = 0;
         pDrvChPrm->deiCropCfg->cropStartY = 0;
@@ -2261,6 +2262,7 @@ Int32 SwMsLink_drvCreateDeiDrv(SwMsLink_Obj * pObj, SwMsLink_DrvObj *pDrvObj)
                 pDrvChPrm->vipScCfg->stripSize = 0;
                 pDrvChPrm->vipScCfg->vsType = VPS_SC_VST_POLYPHASE;
                 pDrvChPrm->vipScCfg->hsType = VPS_SC_HST_AUTO;
+                pDrvChPrm->vipScCfg->enablePeaking = TRUE;
 
                 pDrvChPrm->vipCropCfg->cropStartX = 0;
                 pDrvChPrm->vipCropCfg->cropStartY = 0;
@@ -2306,6 +2308,7 @@ Int32 SwMsLink_drvCreateDeiDrv(SwMsLink_Obj * pObj, SwMsLink_DrvObj *pDrvObj)
                 pDrvChPrm->vipScCfg->stripSize = 0;
                 pDrvChPrm->vipScCfg->vsType = VPS_SC_VST_POLYPHASE;
                 pDrvChPrm->vipScCfg->hsType = VPS_SC_HST_AUTO;
+                pDrvChPrm->vipScCfg->enablePeaking = TRUE;
 
                 pDrvChPrm->vipCropCfg->cropStartX = 0;
                 pDrvChPrm->vipCropCfg->cropStartY = 0;
@@ -2481,6 +2484,7 @@ Int32 SwMsLink_drvCreateScDrv(SwMsLink_Obj * pObj, SwMsLink_DrvObj *pDrvObj)
         pDrvChPrm->scCfg->stripSize = 0;
         pDrvChPrm->scCfg->vsType = VPS_SC_VST_POLYPHASE;
         pDrvChPrm->scCfg->hsType = VPS_SC_HST_AUTO;
+        pDrvChPrm->scCfg->enablePeaking = TRUE;
 
         pDrvChPrm->srcCropCfg->cropStartX = 0;
         pDrvChPrm->srcCropCfg->cropStartY = 0;
-- 
1.7.0.4

    Fullscreen 0728.0001-enabled-peaking-filter-by-default-for-all-scalars_hdvpss.patch.txt Download 
    From 67e9adb57a3a3015c8ae26e73d867e4cfe7e18db Mon Sep 17 00:00:00 2001
From: shiju sivasankaran <a0756868@ti.com>
Date: Thu, 28 Feb 2013 19:38:47 +0530
Subject: [PATCH] enabled peaking filter by default for all scalars

---
 packages/ti/psp/vps/hal/src/vpshalScDefaults.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/packages/ti/psp/vps/hal/src/vpshalScDefaults.h b/packages/ti/psp/vps/hal/src/vpshalScDefaults.h
index dae390d..ea88fd8 100755
--- a/packages/ti/psp/vps/hal/src/vpshalScDefaults.h
+++ b/packages/ti/psp/vps/hal/src/vpshalScDefaults.h
@@ -31,7 +31,7 @@ extern "C"
 /*                           Macros & Typedefs                                */
 /* ========================================================================== */
 
-#if 1
+#if 0
 /* This pre-peaking filter coefficients were designed to peak around 3.3 MHz */
 #define SC_EXPERT_VAL_PEAKING       {0x00u, 0x00u, 0x00u, 0xFCu, 0x00u, 0x08u, \
                                      0x04u, 200, 16, 400, 16, 4}
-- 
1.7.0.4

    Fullscreen 5657.0001-SWMS-correct-coefficient-loading-issue-fixeed-for-se.patch.txt Download 
    From 522d293003a5b8e1e8605721d98a819386372a83 Mon Sep 17 00:00:00 2001
From: shiju sivasankaran <s-sivasankaran1@ti.com>
Date: Thu, 28 Feb 2013 18:14:19 +0530
Subject: [PATCH] SWMS - correct coefficient loading issue fixeed for second scalar instance

---
 mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c |   39 ++++++++++++----------
 1 files changed, 21 insertions(+), 18 deletions(-)

diff --git a/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c b/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c
index 7d86a8b..e6cc412 100755
--- a/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c
+++ b/mcfw/src_bios6/links_m3vpss/swMs/swMsLink_drv.c
@@ -1156,7 +1156,7 @@ Int32 SwMsLink_drvSelectScCoeffs (SwMsLink_Obj * pObj)
     UInt32 inH, outH, inW, outW, numerator, denominator;
     Int32  coeffId_v, coeffId_h;
     Bool isDei;
-    Int32 instId;
+    Int32 instId, i;
 
     /* This is an example of selecting scaling coefficients
 
@@ -1213,24 +1213,27 @@ Int32 SwMsLink_drvSelectScCoeffs (SwMsLink_Obj * pObj)
         }
     }
 
-    instId = 0;
-    if(pObj->DrvObj[instId].isDeiDrv == TRUE)
-        isDei = TRUE;
-    else
-        isDei = FALSE;
-    if (pObj->DrvObj[instId].fvidHandle)
-        SwMsLink_drvSetScCoeffs(pObj, pObj->DrvObj[instId].fvidHandle,
-                                coeffId_v, coeffId_h, isDei);
-
-    instId += SYSTEM_SW_MS_MAX_INST;
-    if(pObj->DrvObj[instId].isDeiDrv == TRUE)
-        isDei = TRUE;
-    else
-        isDei = FALSE;
+    for (i = 0; i < pObj->createArgs.numSwMsInst; i++)
+    {
+        instId = i;
+        if(pObj->DrvObj[instId].isDeiDrv == TRUE)
+            isDei = TRUE;
+        else
+            isDei = FALSE;
+        if (pObj->DrvObj[instId].fvidHandle)
+            SwMsLink_drvSetScCoeffs(pObj, pObj->DrvObj[instId].fvidHandle,
+                                    coeffId_v, coeffId_h, isDei);
+
+        instId += SYSTEM_SW_MS_MAX_INST;
+        if(pObj->DrvObj[instId].isDeiDrv == TRUE)
+            isDei = TRUE;
+        else
+            isDei = FALSE;
 
-    if (pObj->DrvObj[instId].fvidHandle)
-        SwMsLink_drvSetScCoeffs(pObj, pObj->DrvObj[instId].fvidHandle,
-                                coeffId_v, coeffId_h, isDei);
+        if (pObj->DrvObj[instId].fvidHandle)
+            SwMsLink_drvSetScCoeffs(pObj, pObj->DrvObj[instId].fvidHandle,
+                                    coeffId_v, coeffId_h, isDei);
+    }
 
     return FVID2_SOK;
 }
-- 
1.7.0.4

    0001-enabled-peaking-filter-by-default-for-all-scalars.patch.txt

    0001-SWMS-correct-coefficient-loading-issue-fixeed-for-se.patch.txt

    should be applied on dvr_rdl

    0001-enabled-peaking-filter-by-default-for-all-scalars_hdvpss.patch.txt

    should be applied on HDVPSS driver.

    These patches enable peaking filter in HDVPSS and fix a bug in swms when multiple scalers are used .

    If issue is still not resolved after applying the patches pls check the following:

    1. Do you see the same artifacts in the encoded data (CHeck by playing the encoded .h264 stream for say primary channel #0 on a PC player) 

        - Indicates issue with DEI VIP scaler

    2. If you don't see the issue in encoded stream, do you see the issue in playback channel if the same file is fed to mcfw.(Feed encoded frame from channel 0 for playback )

       - Indicates issue with SwMs scaler.

    If you are able to recreate the issue with step #2 pls attach the encoded .h264 file for debug at our end.

  • 0 in reply to Badri Narayanan
    Expert 1460 points

    Hi. Badri. 

    i applied your patch. 

    enable peaking is making the fluorescent light more flickered . i considering do not apply enabled-peaking patch. 

    and when i check the encoded data( Check by playing the encoded .h264 stream for say primary channel #0 on a PC player), i can see the same artifacts . 

    and when i backup and play two RDK(3.0 and 3.5) , 3.0 RDK backuped .h264 stream is more clear.  where can i check in the DEI VIP scaler. 

    can you advice me some testing option at the DEI VIP scaler? 


    thanks for your time and help. 

    BR . CHO. 



  • 0 in reply to kisung cho
    TI__Guru 59700 points

    We checked and the only change in DEI from RDK 3.0 are some enhancements to improve quality in high motion sequences. TO check if this is the reason for the issue can you _revert_ the attached patch from HDVPSS driver package.You have to clean and rebuild RDK after _reverting_ this patch .

    Fullscreen 8233.0001-DEI-setting-Changed-DEI-setting-for-more-2D-oriented.patch.txt Download 
    From 0a89bcc91ecb3a4d686bd67f488749ba64e3b90a Mon Sep 17 00:00:00 2001
From: Naito Tomoyuki <naito@ti.com>
Date: Tue, 27 Nov 2012 19:54:41 +0800
Subject: [PATCH 1/1] [DEI setting] Changed DEI setting for more 2D oriented.
 This results in better quality in fast motion.


Signed-off-by: Brijesh Jadav <Brijesh.Jadav@ti.com>
---
 packages/ti/psp/vps/hal/src/vpshalDeiDefaults.h  |    6 +++---
 packages/ti/psp/vps/hal/src/vpshalDeihDefaults.h |    6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/packages/ti/psp/vps/hal/src/vpshalDeiDefaults.h b/packages/ti/psp/vps/hal/src/vpshalDeiDefaults.h
index c9ca920..9987ccf 100755
--- a/packages/ti/psp/vps/hal/src/vpshalDeiDefaults.h
+++ b/packages/ti/psp/vps/hal/src/vpshalDeiDefaults.h
@@ -40,10 +40,10 @@ extern "C" {
 /* Todo: Update with recommended values from DEI IP team */
 #define VPSHAL_DEI_DEFAULT_EXPERT_VAL                                          \
 {                                                                              \
-    0x020C0804u,                /* Expert value for DEI REG2 register */       \
+    0x00201610u,                /* Expert value for DEI REG2 register */       \
     0x0118100Fu,                /* Expert value for DEI REG3 register */       \
-    0x08040200u,                /* Expert value for DEI REG4 register */       \
-    0x1010100Cu,                /* Expert value for DEI REG5 register */       \
+    0x100c0a06u,                /* Expert value for DEI REG4 register */       \
+    0x10101010u,                /* Expert value for DEI REG5 register */       \
     0x10101010u,                /* Expert value for DEI REG6 register */       \
     0x10101010u,                /* Expert value for DEI REG7 register */       \
     0x080A0000u,                /* Expert value for DEI REG10 register */      \
diff --git a/packages/ti/psp/vps/hal/src/vpshalDeihDefaults.h b/packages/ti/psp/vps/hal/src/vpshalDeihDefaults.h
index 9e32112..9b78527 100755
--- a/packages/ti/psp/vps/hal/src/vpshalDeihDefaults.h
+++ b/packages/ti/psp/vps/hal/src/vpshalDeihDefaults.h
@@ -41,7 +41,7 @@ extern "C" {
 #define VPSHAL_DEIH_DEFAULT_EXPERT_VAL                                         \
 {                                                                              \
     0x0C110142u,                /* Expert value for MDT CFG0 register */       \
-    0x820C0804u,                /* Expert value for MDT CFG1 register */       \
+    0x00201610u,                /* Expert value for MDT CFG1 register */       \
     0x20302010u,                /* Expert value for MDT CFG2 register */       \
     0x140C0404u,                /* Expert value for MDT CFG3 register */       \
     0x50030804u,                /* Expert value for MDT CFG4 register */       \
@@ -53,8 +53,8 @@ extern "C" {
     0x401E1010u,                /* Expert value for EDI CFG1 register */       \
     0x01000032u,                /* Expert value for EDI CFG2 register */       \
     0x18201219u,                /* Expert value for EDI CFG3 register */       \
-    0x08040200u,                /* Expert value for EDI CFG4 register */       \
-    0x1010100Cu,                /* Expert value for EDI CFG5 register */       \
+    0x100c0a06u,                /* Expert value for EDI CFG4 register */       \
+    0x10101010u,                /* Expert value for EDI CFG5 register */       \
     0x10101010u,                /* Expert value for EDI CFG6 register */       \
     0x10101010u,                /* Expert value for EDI CFG7 register */       \
     0x06020602u,                /* Expert value for TNR CFG1 register */       \
-- 
1.7.0.4

  • 0 in reply to Badri Narayanan
    Expert 1460 points

    Hi Badri.

    after reverted your patch. 45 degree's line displayed clearly and there's no more atrifacts. 

    in addition to when i test 960H mode, not reverted DEI  more noticeable and not good .

    i think if you have a chance to use another 960H supported video decoder, you can see it's serious. 


    because we have a exhibition,   your support much helped for us. 

    thank you for your time and help. 

     Best Regards. CHO