C66xx register access cycle

UNA

Hello,

I have been made to the benchmark test of SRIO on C667x.

I think it takes a long time to register access.

I measured the two registers in the following way.

(PLL1 Setup for DSP @ 1000.0 MHz and 'data' was placed in the L2SRAM. )

**** old = TSCL;

data = *(volatile unsigned int*)0x02900D18; <--- LSU1_REG6

now = TSCL; cycletime = now - old;

old = TSCL;

data = *(volatile unsigned int*)0x02900DE8;　　<--- LSU_STAT_REG0

now = TSCL;

cycletime = now - old;

****

The result is as follows.

LSU1_REG6 register access cycle : 76 cycle

LSU_STAT_REG register access cycle : 113 cycle

So, I have a question, is this result reasonable ?

Best Regards,

Chi

0 Chad Courtney over 12 years ago

Chi,

Register are on a separate bus, which is a relatively slow bus as they are not accessed frequently. That said, this does seem a little large.

You should also determine the turnaround delay of performing the TSCL reads.

old = TSCL;

now = TSCL;

Overhead = now - old.

Then when you calculate the time, you can removed the overhead as well.

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