McAsp ASYNC=0 RX signal delay

Jan,

Which DSP are you using?

The relationships of the signals are shown in the peripheral's User Guide or the datasheet. In some devices, these can be controlled using peripheral configuration registers.

It is common to sample any signal in the middle of its valid width.

Regards,
RandyP

Hi,

I use the McAsp3 of the TMS320C674x. In the document SPRS778E chapter 8.15 I found some timing figures. But I am not sure if this is also valid in synchronous mode because the CLKRP has no effect so far I know and RCLK is inverted relating to XCLK. In the actual configuration I set CLKXP=1 and I can measure the transmit signal is shifted out at falling edge and valid at rising edge. So lets take a look at Figure 8-79 (McASP Input Timing) in SPRS778E to analyze the receive signal. Case (B) shows MCA[x]_ACLKR/X  if CLKRP = CLKXP = 1. Is this the right CLK signal? Do I have to set CLKRP to 1, too? This would mean that no delay should be between transmit and receive bits. Is this correct?

Regards

Jan

Jan,

Which device are you using? C674x is not a device, but a family of processor cores or devices.

I have not heard of a McAsp3, so it may help a lot when I can learn which specific device you are using?

The SPRS778 document is not available to me on my searches. Is this device one that is not publicly supported?

Perhaps someone else can help you.

Regards,
RandyP

Hi, I also don't recognize the documents that you're referring to, so it's hard to tell what device you need support on.  But in general, if one device transmits data on the rising edge of the bit clock, then other device should receive on the falling edge.  And vice versa.

Synchronous mode just means that for a given instance of McASP (let's call it McASPn), McASPn Rx uses McASPn Tx's clocks, though RCLK is inverted with respect to XCLK as you noted.  This can be useful if you have synchronous input and output and want to use one McASP for both; the inversion you mentioned is there so that, as I described, you'd be receiving on one edge and transmitting on the other.

You said that the external controller is the master, so I guess it's generating clocks.  So you're sending data from that controller to McASPn Rx, and then sending it back to that controller using McASPn Tx section?  If yes, sync mode makes sense.  You'd feed those clocks to the transmitter (AHCLKXn, ACLKXn, AFSXn) and set ASYNC = 0 as you said.  When you ask about delaying Rx signals by half a cycle, what signals do you mean?  I don't believe that you have to do anything other than configure the clocks as discussed, and make sure that the external controller is set to accept and transmit data on the appropriate edges.

"You said that the external controller is the master, so I guess it's generating clocks.  So you're sending data from that controller to McASPn Rx, and then sending it back to that controller using McASPn Tx section?  If yes, sync mode makes sense."

-> Yes, this is I want to do.

"You'd feed those clocks to the transmitter (AHCLKXn, ACLKXn, AFSXn) and set ASYNC = 0 as you said.  When you ask about delaying Rx signals by half a cycle, what signals do you mean?  I don't believe that you have to do anything other than configure the clocks as discussed, and make sure that the external controller is set to accept and transmit data on the appropriate edges."

The problem is that the external controller can only sample the data at the rising edge (McAsp shifts out at falling edge)  and the data from the external controller can only shifted out at falling edge so the McAsp had to sample at rising edge. But because of the CLK inversion this requirement can not be met.

conclusion: McAsp shifts data out at falling edge and external controller shifts out data at falling edge. So I can not measure a phase difference (delay between MSB of RX and TX data at the wire beween external controller and McAsp). But in this constellation I sample the RX signal at the edges in the McAsp. So I think a phase difference (delay of half CLK cycle) have to be there and we have to insert a FlipFlop in the RX signal between external controller and McAsp.