unaligned access am3703

Alexander,

Looks like compiler has not at all generated the aligned access code. But may because the GCC attributes may not be supported by the toolchain. Can you try to refer to TMS470 compiler user guide on how to give compiler attributes to the compiler?

Thanks for your answer.

Compiler generate code, understanding that proccessor can support unaligned access, isn't it? Can you explain, what mean - "not at all generated the aligned access code"? So, you think - problem with compiler, not proccessor?

I am use only CCSv5.3. What GCC attributes may be not supported by the toolchain - "packed"? It's work, size of such struct is 7, that is true. But this attribute work, only if I set "Enable support for GCC extensions (--gcc)" in project properties in CCS, else compiler return some errors. I read about gcc extensions support at TI_wiki. I don't see some mistakes or errors in this part.

And the last you suggestion I don't understand - I see, that version compiler TI-5.0.1 and use "ARM optimizing C\C++ Compiler v5.0 User's Guide" (spnu151h), read it week ago. There is "--unaligned-access" option for enable\disable generate different access code, but guide says, that for Cortex proccessors it is always "ON".

Alexander,

ARM processor doesn't support unaligned access. The compiler still supports unaligned access by generating multiple load/store instructions instead of a single load/store instruction. 

I have pasted the code that is generated by gcc with -O2 set. Compare it with the code that you got. 

@ args = 0, pretend = 0, frame = 0
@ frame_needed = 0, uses_anonymous_args = 0
@ link register save eliminated.
ldr r3, .L3
mov r2, #17
mov r0, #119
mov ip, #68
strb r2, [r3, #6]
mov r1, #34
mov r2, #51
strb r0, [r3, #1]
strb r0, [r3, #0]
strb ip, [r3, #3]
strb r2, [r3, #4]
strb r1, [r3, #5]
strb ip, [r3, #2]
mov r0, #0
bx lr

Hm...guides&TRM says that CortexA8 support unaligned access, and i think - this is reason why CCS compiler don't try to generate multiple load\store instructions...

maybe i'm wrong...

Thanks, you code look workable, many strb, it is good. But my code with -O2 same like without optimization, compiler use strb, strh..instead many strb :(

         main:
40200c2c:   E59FC01C LDR             R12, $C$CON1
40200c30:   E3A00077 MOV             R0, #119
40200c34:   E5CC0000 STRB            R0, [R12]
32            mystruct.X = 0x4477;
40200c38:   E3040477 MOVW            R0, #17527
40200c3c:   E1CC00B1 STRH            R0, [R12, #0x1]
33            mystruct.Y = 0x11223344;
40200c40:   E59F000C LDR             R0, $C$CON2
40200c44:   E58C0003 STR             R0, [R12, #3]
35            return 0;
40200c48:   E3A00000 MOV             R0, #0
40200c4c:   E12FFF1E BX              R14

TI "ARM compiler guide" says about  "--unaligned_access" option - "This option is on by default for all Cortex devices", so it's look like no way to generate code from CCScompiler with strb instructions use only.

Renjith Thomas,

yes, issue resolved, thanks for your help.