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DM814x McASP ports asynchronous clocking

Martin Tanguay
Prodigy 225 points

Hi,

My application requires to have 3 McASP ports with 3 different clock domains.  For each port, the Rx/Tx are synchronous to each other, but each port clocking is asynchronous to the other.  The clock for each port will be given by an FPGA.

On page 318 of the datasheet, it says that McASP0 and McASP1 have separate clocking and McASP 2/3/4/5 share the same clock.

If my assumption is correct, this means I could use McASP0/1/2 in 3 different clock domains, i.e. driving clock0 to McASP0, clock1 to McASP1 and clock2 to McASP2

Are my assumptions correct ?  Would it work ?

Thanks.

Martin Tanguay

  • 0
    TI__Guru**** 170625 points

    Hi Martin,

    Yes, you can deliver three different clock signals (aux_clk) from the device PRCM to these three McASP instances: in example sysclk20 -> McASP0, sysclk21 -> McASP1 and sysclk22 -> McASP2

    This can be done by programming the following registers:

    CM_AUDIOCLK_MCASP0_CLKSEL[1:0] CLKSEL = 0x0 (select sysclk20)

    CM_AUDIOCLK_MCASP1_CLKSEL[1:0] CLKSEL = 0x1 (select sysclk21)

    CM_AUDIOCLK_MCASP2_CLKSEL[1:0] CLKSEL = 0x2 (select sysclk22)

    Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 225 points

    Thanks for the reply.  I forgot to mention that the 3 clock domains would come from an FPGA, so these clocks are external to the CPU.

    Will it still work ?

    Thanks.

  • 0 in reply to Martin Tanguay
    TI__Guru**** 170625 points

    If you mean that you are planning to use the McASP modules in slave mode (supply clock signals from external source (FPGA) to the aclkx/r and ahclkx/r pins, instead of supply clock signals internally from the device PRCM) with different clock signals to McASP0/1/2 aclkx/r and ahclkx/r pins, I do not see any obstacles and I think this should work. We can supply the McASP0/1/2 from three different internal clock sources (sysclk20/21/22) so I think we can supply the McASP0/1/2 from three different external clock sources as well. See DM814x TRM, section 16.2.2 Clock and Frame Sync Generators

    Regards,

    Pavel

  • 0
    TI__Guru**** 170625 points

    Martin Tanguay said:
    On page 318 of the datasheet, it says that McASP0 and McASP1 have separate clocking and McASP 2/3/4/5 share the same clock.

    This is what we have there:

    The device includes six multichannel audio serial port (McASP) interface peripherals (McASP0, McASP1, McASP2, McASP3, McASP4, and McASP5). The McASP module consists of a transmit and receive section. On McASP0/1, these sections can operate completely independently with different data formats, separate master clocks, bit clocks, and frame syncs or, alternatively, the transmit and receive sections may be synchronized. On McASP2, McASP3, McASP4, and McASP5, the transmit and receive sections must always be synchronized. The McASP module also includes shift registers that may be configured to operate as either transmit data or receive data.

    This is how I understand this text:

    McASP0 and McASP1 can use one clock for the TX section (either supplied externally or internally) and other clock for RX section (either supplied externally or internally).

    McASP2/3/4/5 must use the same clock for the RX and TX sections.

    All McASP modules (McASP0/1/2/3/4/5) can use different clock signals  (either supplied externally or internally), for their RX/TX sections.

    Regards,

    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 225 points

    Thanks Pavel, it answers my question.

    Best regards.