Hi,
in [PCIE_SERDES_CFGPLL] config, the default value is 0x000001C9, so that will Enable DIVCLK output and enable output of a divide by-5 of PLL clock.
Tis dividing will affect others config?? and where we can use/non use this dividing???
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Hi,
in [PCIE_SERDES_CFGPLL] config, the default value is 0x000001C9, so that will Enable DIVCLK output and enable output of a divide by-5 of PLL clock.
Tis dividing will affect others config?? and where we can use/non use this dividing???