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How to Change DPLL5 setting of DM3730?

zhang liuyang
Prodigy 80 points
Other Parts Discussed in Thread: DM3730

We have a board designed with with DM3730.But we have great trouble woth USB system.It consists as follows:

DM3730--->USB3320---->AU6656-------3G +WIFI module.

And we are sure after a complter power offtime(5-10minutes),power up then we can see we lost device or HUB by using lsusb command.

when everything is ok,we can see four devices with LSUSB command.

After doing some google and searching in the support forum,we found the followering is at our interest.

Advisory 2.1 in the latest errata starts to explain the issue with PLL registers and drift.  We were having further trouble as the values we thought we were setting were getting over written by an automated routine. After changing the master clock to 38.4MHz from 26MHz and setting up the DPLL5 registers recommended in the errata we are solid at all temperatures.

http://www.ti.com/lit/er/sprz319e/sprz319e.pdf

So how can we change the DPLL5 setting?change what file?in Uboot or in the kernel source code?

thanks in advance!

  • 0
    TI__Guru 65405 points

    Hi Zhang,

    There are several registers which affects DPLL5 (PRM_CLKSEL, CM_CLKEN2_PLL, CM_CLKSEL4_PLL, ...). You could read in the TRM chapter 3.6 PRCM Basic Programming Model and pay attention on the 3.6.2 Clock Management Registers. Read also 3.7 PRCM Register Manual.

    http://www.ti.com/lit/ug/sprugn4r/sprugn4r.pdf

    It is very important to set proper DPLL5 configuration in the kernel. The files ...linux../arch/arm/mach-omap2/clock3xxx.c and clock3xxx_data.c contains functions and structures related to DPLL5. It should be useful to make configuration and in the u-boot but this will take effect only until kernel complete booting. One good place is u-boot board file foe example .../u-boot../board/ti/evm/evm.c.

    BR

    Tsvetolin Shulev

  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 80 points

    I've changed the code in /arch/arm/mach-omap2/dpll.c

    struct dpll_settings {
        int rate, m, n, f;
    };

    static const struct dpll_settings precomputed[] = {
            /* From DM3730 errata (sprz319e), table 36
            * +1 is because the values in the table are register values;
            * dpll_program() will subtract one from what we give it,
            * so ...
            */
            { 13000000, 443+1, 5+1, 8 },
            { 26000000, 443+1, 11+1, 8 }
    };

     int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)

    //zly add for DPLL5 configuration
            const struct dpll_settings *d = &precomputed[1];//for 26Mhz crystal
                    //clk setting
            dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
            rv =  omap3_noncore_dpll_program(dpll5_m2_clk, d->m , d->n, 0);
            //if (ret)
            //    return 1;
            rv=  omap2_clksel_force_divisor(dpll5_m2_clk, d->f);///?

    then i make the uImage,burn it,the new kernel can't boot.

    according to the patch below:

    https://github.com/Angstrom-distribution/meta-ti/blob/master/recipes-kernel/linux/linux-3.0/usb/0001-Fix-sprz319-erratum-2.1.patch

    as 26Mhz is our main clock source,i want to change the DPLL5 to

            { 26000000, 443+1, 11+1, 8 }

    how to do that?

  • 0 in reply to zhang liuyang
    Prodigy 80 points

    HFCLKOUT is 60Mhz.

    After change the code,The measured frequency of USB1HS_CLK is 30.0625MHZ.

    static const struct dpll_settings precomputed[] = {

    /* From DM3730 errata (sprz319e), table 36

    * +1 is because the values in the table are register values;

    * dpll_program() will subtract one from what we give it,

    * so ...

    */

    { 13000000, 443+1, 5+1, 8 },

    { 26000000, 443+1, 11+1, 8 }

    };

    //zly add for DPLL5 configuration

    const struct dpll_settings *d = &precomputed[1];//for 26Mhz crystal

                    //clk setting

    dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");

    rv =  omap3_noncore_dpll_program(clk, d->m , d->n, 0);//zly

    //if (ret)

    // return 1;

    rv=  omap2_clksel_force_divisor(dpll5_m2_clk, d->f);///?

    If we want to revised according to the Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Configurations

    Revision(s) Affected 1.2, 1.1 and 1.0 in page 112 .Sprz319e,how to do that?

    Is the register value corrected?{ 26000000, 443+1, 11+1, 8 }

  • 0 in reply to zhang liuyang
    Prodigy 80 points

    After discuss USB3320 with tech support resource,now i can confirm the usb3320 random enter power down mode,the EHCI enter bypass mode, stop  USB communication.is there a workaround or patch available?The kernel is 2.6.32.