About VIP configuration

qing maxwell

I'm using vip0 parser portA to capture single 16bit yuv 422 video , vip1 to capture 8 bit video, they are both embed sync.

Vip1 works but vip0 not.

Vip0 main (address offset 0x5500): 0x1

Vip0 portA (address offset 0x5504): 0xa110

Vip0 fiq status (address offset 0x551c): 0x30004, and some time it was 0x0, or 0x4

So, is there anything I can do to fix the problem?

Thanks and regards,

maxwell

over 12 years ago

0 Brijesh Jadav over 12 years ago

TI__Guru**** 480505 points

Hi,

This error means that you input is not connected properly and SAV/EAV bits are toggling correcly. Could you please check if input side, it is correct?

Regards,

Brijesh Jadav

0 qing maxwell over 12 years ago in reply to Brijesh Jadav

Prodigy 80 points

Thanks for your reply. According to the data sheet of dm8167, Register VIP0 FIQ Status 31:10 are reserved and always read as 0. But I found it changed, so I want to know whether some of the reserved bits have specific information.

0 HardikShah over 12 years ago in reply to qing maxwell

TI__Mastermind 20245 points

Hi,

Those bits are reserved for most of the devices. While few devices has some meaning. Please contact your local TI FAE to know more about them.Register details are under NDA and this is not the correct forum to share it.

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