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PCIe DSPC6678, No Data sent

Delared Delared
Expert 1945 points

Object: Communication PCIe between DSP as RC and DSP as EP via BOC

Hi,

in the example: C:\Program Files\Texas Instruments\pdk_C6678_1_0_0_17\packages\ti\drv\pcie\example\sample\pcie_sample.c

the EP did config successfully and wait for link training..

at the same, RC did config => link is up..

So in this step we have a problem, basically the RC will send data to EP

/* Wait for a single message from the RC then echo it back */

 /* EP waits for the data received from RC */

so we are blocked here??!!!!...and we cannot reach:

"End Point received data.\n"

"End Point sent data to Root Complex, completing the loopback.\nEnd of Test"

  • 0
    TI__Genius 12065 points

    Did you put both RC and EP EVMs in no-boot mode please?

    The PCIe PDK example will configure the device in the desired mode based on the following setup in your source code:

    pcieMode_e PcieModeGbl = pcie_EP_MODE;  //or pcie_RC_MODE

    Do you get the "link up" message on both RC and EP please?

    And which exact line are you block at in each of your RC and EP program?

  • 0 in reply to Steven Ji
    Expert 1945 points

    Steven,

    1-  Both RC and Ep EVMs is in no-boot mode:

    §SW3=0001   =>emulation Boot
    §SW4=00000  => I2C Boot (default, Not used)
    §SW5=0000  =>I2C Boot (default, Not used)
    §SW6=0000  => PCIe EP Mode [DSP2]

     § SW6=1000  => Root Complex Mode[DSP1]

    §SW9=11  =>PCIe module enabled, application software defined

    2- "Link is up" in both RC & EP.

    3- the RC is blocked here:

     /* Data sent to EP.
           RC waits for the loopback to be completed and
           receive data back from EP */

        do {
          unsigned int key;

          /* Disable Interrupts */

    .....

    4- EP is blocked here:

    /* EP waits for the data received from RC */
        do {
          unsigned int key;

          /* Disable Interrupts */
          key = _disable_interrupts();

          /*  Cleanup the prefetch buffer also. */
          CSL_XMC_invalidatePrefetchBuffer();

    .....

    its seems that RC sent data but the EP cannot receive it!!!

  • 0 in reply to Delared Delared
    TI__Genius 12065 points

    Have you done any modification to the example code please?

    If not, could you please see if you follow the sequence below for the testing:

    1. Power up both EVMs and connect CCS to Core0 (or Core1) on each board 

    2. Do "System Reset" on the connected CorePac, PC will be pointed to 0x20B00000

    3. Load "evmc6678l.gel" file (C:\ti\mcsdk_2_01_02_05\tools\program_evm\gel) on connected CorePac

    4. Execute "EVMC6678L Init Functions" -> "Global_Default_Setup" under Scripts menu

    5. Load test case to the CorePac (RC on one EVM and EP on the othe EVM)

    6. Run the test cases on both EVMs (no matter run RC first or EP first)


    It seems to be a cache issue. When the program is stuck, could you check "dstBuf" in the CCS memory view on EP side to see if any data being transferred from RC?

    Please make sure to disable the L1/L2 cache in the memory view window.

    I hope the system reset and using GEL file could initialize the CorePac cache properly.