• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 99 subscribers
  • Views 1180 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM3359 McASP I2S tx delay bit

Chris Conley
Prodigy 80 points
Other Parts Discussed in Thread: OMAP-L138

I am trying to get a mono codec up and running (WM8974, mono, no register read available) on a custom board (with WEC7) and I'm having an issue with the tx delay bit.

If I add the 1-bit delay in, as required by the I2S timing, the frame sync isn't taking it into account, so the LSB is written to the other channel (see img).

I have the McASP0 as the master using the 25MHz AUXCLK, and the issue shows up with any sample rate I tried. The only way to get it to fit is to have a 0-bit delay, which I think the codec doesn't like (it starts muting the output port).  I tried setting the SR output to 20bits, which stopped the leaking, but I doubt that is working for the codec receiver end.

20-bit config: (16-bit has the AHCLKXDIV at 9 instead of 7)

WFIFOCTL 0x00010101

FMT             0x00018094
AFSCTL      0x00000113
ACLKCTL   0x001800a7
CLKCHK        0x00ff0008

AHCLKCTL 0x00188006

XMASK        0x0000FFFF

I've dug through all the OMAP-L138 and DSP e2e posts, and looked at the ALSA code, and SW code and I don't see anything that looks different from what I'm doing in the setup of the clocks.

Any assistance in tracking this issue down would be greatly appreciated!

//Chris

  • 0
    TI__Genius 15910 points

    Hi Chris,

    The waveform you show is an expected output from a 1-bit delay. See Figure 22-9 (TDM Format Bit Delays from Frame Sync) of the TRM.

    The WM8974 datasheet mentions that in I2S mode, it expects that "depending on word length, BCLK frequency, and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next."  You might try configuring the McASP for 1-bit delay and set the slot size larger than is actually needed.  Using the XMASK register, you can mask the extra, unwanted bits and thereby pad the slot with a known value (defined by the XPAD bitfield in XFMT).

    Regards,
    Melissa

  • 0 in reply to melissaw
    Prodigy 80 points

    Hi Melissa,

    That was the reason why I tried the 20-bit XMASK before was to try and match that figure.  

    I've reverted the settings to the 20-bit version and I'm getting the waveform that is expected:

    Thank you for the corroboration!  Given I was originally having issues with McASP<->EDMA3 as well as I2S frame setup, it was hard to discern which thing was actually broken.  I shall concentrate on the DAC not rendering to the output port and not worry about the data format going in.

    Out of curiosity, how would 32-bit sample sizes be done with I2S? Is it possible, or would I need to change to a justified frame format?

    //Chris