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Cache coherence, PCIe example\sample C6678

Delared Delared
Expert 1945 points

Hi,

In the example: C:\Program Files\Texas Instruments\pdk_C6678_1_0_0_17\packages\ti\drv\pcie\example\sample

I can’t understand:

1-      In the header pcie_sample.h (line 99) we have:

/* BAR mask */

#define PCIE_BAR_MASK         0x0FFFFFFF  

But in pcie.sample.c (line 80) I found:

/* cache coherence:Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address  */

#pragma DATA_ALIGN(dstBuf, 256)

/* last element in the buffer is a marker that indicates the buffer status: full/empty */

#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 128

So the PCIE_BAR_MASK is 256 Mbytes, ALIGN(dstbuf is 256 bytes and MAX_CACHE_LINE_SIZE is 128 bytes!!! Please I need more explanations!

2-      Line 104: extern volatile unsigned int cregister TSCL:

 what is Cregister ???, and where is declared??

  • 0
    TI__Intellectual 2180 points

    Delared Delared said:

    But in pcie.sample.c (line 80) I found:

    /* cache coherence:Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address  */

    #pragma DATA_ALIGN(dstBuf, 256)

    The comment above doesn't match the code.  The actual comment is:

    /* Cache coherence: Align must be a multiple of cache line size (L2=128 bytes, L1=64 bytes) to operate with cache enabled. */
    /* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address  */

    This means that if you place the buffer in MSMC memory or anywhere only cachable in L1D, then you need to align to at least 64 bytes for L1D.

    If you place the buffer in DDR memory or anywhere cachable by both L1 and L2, then you need to align to at least 128 bytes.

    Due to alignment of inbound address translation, you need to align to at least 256 bytes.

    Thus, the max of the 3 is 256 bytes, so we aligned it to 256 bytes.

    Delared Delared said:

    2-      Line 104: extern volatile unsigned int cregister TSCL:

     what is Cregister ???, and where is declared??

    This is TI specific.  It allows the compiler to access CPU registers.  In this case, TSCL is a register that counts once per cycle, once it is activated by any write.

    It is documented in the compiler user's guide.  A copy can be found in c:\ti\ccsv5\tools\compiler\c6000\doc\SPRU187T.pdf.  (last letter before .pdf can change), or wherever you installed ccs.  It is in section 6.5.2 of the users guide.