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add delay between DMA accesses using EDMA3

Other Parts Discussed in Thread: TMS320C6745

I am using the TMS320C6745 and setting up a DMA to a DDC 1553 device, the Total-ACE via EMIFA.  I need to transfer 64 bytes so I set up an A-synchronized DMA. This device requires a delay after every other byte.  I adjusted the EMIFA timing as much as possible with the Asynchronous Configuration register, but I am still getting less than a 1% error rate. 

I tried breaking up the transfer into 32 2 byte transfers using the example described in 16.3.4.5.2 of SPRUH91A, but I could not get it to work at all.  How much delay would this introduce?  Can you provide a more detailed description of how to program the Parameter set?

Is there another approach that would provide around 100ns of delay after every second byte?

Rick

  • Richard,

    The EDMA3 is not designed to normally insert delays. It will respond to an event and transfer the required data as soon as possible after that event.

    What event are you using to trigger the DMA channel? Which pin and what device is generating that signal?

    Please describe more about the A-synchronized transfer and what you need the delay to provide.

    Regards,
    RandyP

  • I am doing a manually triggered DMAs based on an external interrupt source that occurs at 3600Hz.

    I want to transfer 64 bytes by inserting a 100ns to 200ns delay after every second byte.  That is, transfer 2 bytes with no delay and then insert a delay and then transfer 2 more bytes with no delay, repeating  until 64 bytes have been read.

    I found the RDRATE register in the Transfer Controller.  Is this a possibility?

  • Richard,

    Is the EMIF interface to the device 8 bits wide or 16 bits wide?

    Are you sending sequential data from DSP memory to incrementing addresses in the DDC, or to a fixed address? If fixed, how many bytes go to that address at a time?

    Will the RDRATE (Read Rate Register) control the write rate? No. The text in the EDMA3 User Guide Section 2.14.3 states this.

    Regards,
    RandyP

  • The EMIF interface is 8 bits.

    I am reading data from incrementing addresses on the device.

  • You are reading, not writing?

    Then it would be worth a try to test the RDRATE register. I am not sure it will give the effect that you want, though, because it works by spacing out internal commands which are sized based on the DBS (Default Burst Size) parameter for a bus or peripheral. I am not sure what the EDMA3 clock rate is, so I am not sure what the result will be for the various settings for your delay.

    The proper way to do this is to have an event coming to the EDMA3 that would request each 2-byte pair, and that event signal would have the spacing that you want. 200ns is pretty fast, though, so that might not be a clean solution from a pin.

    Another idea would be to use chaining to send 2 bytes from the main DMA channel, then chain to another channel that does some other unnecessary transfer to a different EMIF space or a different memory or peripheral, and then chain back to the main DMA channel for the next transfer.

    All of this is getting pretty complex, though, so if the simple RDRATE works for you, great. If not, you will want to go to the Training section of TI.com. There is a training video set for the C6474. It may be helpful for you to review several of the modules, but in particular, the EDMA3/QDMA/IDMA Module may help you understand some of the features and options available within the EDMA3 module. You can find the complete video set here.

    Regards,
    RandyP