Other Parts Discussed in Thread: OMAP-L138
Hi:
I am using the OMAP-L138,and I would like to operate the USB OTG as a host by the ARM side,maybe I have did something wrong during initializing the USB OTG module,so something strange happended.The initialize code as follows.
//----------------------------------------------------------------------------
// \brief Configure the USB module for OTG mode.
//
// \return none.
//-----------------------------------------------------------------------------
void USB_OTG_init()
{
uint16_t I;
// **************************************************************************
// Configure DRVVBUS Pin to be used for USB
// **************************************************************************
// MAKE SURE WRITE ACCESS KEY IS INITIALIZED PRIOR TO ACCESSING ANY OF THE
// BOOTCFG REGISTERS.
// SYSCONFIG->KICKR[0] = KICK0R_UNLOCK;
// SYSCONFIG->KICKR[1] = KICK1R_UNLOCK;
// CONFIGURE THE DRVVBUS PIN HERE.
//See your device-specific System Reference Guide for more information on how to set up the pinmux.
usbotg_isr_init();
// Power up the USB HW.
EVMOMAPL138_lpscTransition(PSC1, DOMAIN0, LPSC_USB0, PSC_ENABLE);
// Power up the USB HW.
// Reset the USB controller:
USB_OTG->CTRLR |= 0x00000001;
//Wait until controller is finished with Reset. When done, it will clear the RESET bit field.
while ((USB_OTG->CTRLR & 0x1) == 1);
// RESET: Hold PHY in Reset
SYSCONFIG->CFGCHIP[2] |= 0x00008000; // Hold PHY in Reset
// Drive Reset for few clock cycles
for (I=0; I < 50; I++);
// RESET: Release PHY from Reset
SYSCONFIG->CFGCHIP[2] &= 0xFFFF7FFF; // Release PHY from Reset
// Configure PHY with the Desired Operation
// OTGMODE
SYSCONFIG->CFGCHIP[2] &= 0xFFFF9FFF; // 00= > Do Not Override PHY Values
// SYSCONFIG->CFGCHIP[2] |= (0x01 << 13); // 01 = > Override PHY Values,force host operation
// SYSCONFIG->CFGCHIP[2] |= 0x00002000; // 11= > Override PHY Values, force host, VBUS low
// PHYPWDN
SYSCONFIG->CFGCHIP[2] &= 0xFFFFFBFF; // 1/0 = > PowerdDown/ NormalOperation
// OTGPWRDN
SYSCONFIG->CFGCHIP[2] &= 0xFFFFFDFF; // 1/0 = > PowerDown/ NormalOperation
// SYSCONFIG->CFGCHIP[2] |= (1 << 9); // PowerDown
// DATAPOL
SYSCONFIG->CFGCHIP[2] |= 0x00000100; // 1/0 = > Normal/ Reversed
// SESNDEN
SYSCONFIG->CFGCHIP[2] |= 0x00000020; // 1/0 = > NormalOperation/ SessionEnd
// SYSCONFIG->CFGCHIP[2] &= 0xFFFFFFEF;
// VBDTCTEN
SYSCONFIG->CFGCHIP[2] |= 0x00000010; // 1/0 = > VBUS Comparator Enable/ Disable
// Configure PHY PLL use and Select Source
// REF_FREQ[3:0]
SYSCONFIG->CFGCHIP[2] |= 0x00000002; // 0010b = > 24MHz Input Source
// USB2PHYCLKMUX: Select External Source
// SYSCONFIG->CFGCHIP[2] &= 0xFFFFF7FF; // 1/0 = > Internal/External(Pin)
SYSCONFIG->CFGCHIP[2] |= 0x00000800;//Bit11 Internal clock from AUXCLK
// PHY_PLLON: On Simulation PHY PLL is OFF
SYSCONFIG->CFGCHIP[2] |= 0x00000040; // 1/0 = > On/ Off
// Wait Until PHY Clock is Good
while ((SYSCONFIG->CFGCHIP[2] & 0x00020000) == 0); // Wait Until PHY Clock is Good.
#ifndef HS_ENABLE
// Disable high-speed
//CSL_FINS(USB_OTG->POWER,USB_OTG_POWER_HSEN,0);
USB_OTG->POWER &= ~USB_OTG_POWER_HSEN;
#else
// Enable high-speed
//CSL_FINS(usbRegs->POWER,USB_OTG_POWER_HSEN,1);
USB_OTG->POWER |= USB_OTG_POWER_HSEN;
#endif
// Enable Interrupts
// Enable interrupts in OTG block
USB_OTG->CTRLR &= 0xFFFFFFF7; // Enable PDR2.0 Interrupt
USB_OTG->INTRTXE = 0x001F; // Enable All Core Tx Endpoints Interrupts + EP0 Tx/Rx interrupt
USB_OTG->INTRRXE = 0x001E; // Enable All Core Rx Endpoints Interrupts
// Enable all interrupts in OTG block
USB_OTG->INTMSKSETR |= 0x01FF1E1F;
// Enable all USB interrupts in MUSBMHDRC(Excpet the SOF interrupt)
USB_OTG->INTRUSBE = 0xFF;
// Enable SUSPENDM so that suspend can be seen UTMI signal
//CSL_FINS(USB_OTG->POWER,USB_OTG_POWER_ENSUSPM,1);
// USB_OTG->POWER |= USB_OTG_POWER_ENSUSPM;
//Clear all pending interrupts
USB_OTG->INTCLRR |= USB_OTG->INTSRCR;
// Start a session
//CSL_FINS(USB_OTG->DEVCTL,USB_OTG_DEVCTL_SESSION,1);
USB_OTG->DEVCTL |= USB_OTG_DEVCTL_SESSION;
}
/**
**
** Register the interrupt handler
**
**/
void usbotg_isr_init(void)
{
//Interrupt Channel
aintcRegs->CMR14 |= 0x000A0000;
//Register Interrupt Routine
AddISR(58,usbotg_isr_handler,(void*)0);
//Enable USB Interrupt
aintcRegs->EISR = 58;
}
/**
**
** Interrupt Service Routine
**
**/
void usbotg_isr_handler(uint32_t vector,uint32_t arg)
{
unsigned int ulStatus;
unsigned char RxFIFO[100];
unsigned char RxIdx = 0;
ulStatus = USB_OTG->INTSRCR;//Get the Interrupt Source
USB_OTG->INTCLRR = ulStatus;//Clear Interrupt Source
if (ulStatus & USB_OTG_INTSRCR_RESUME)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_RESUME;
USB_DBG("ISR:RESUME\n");
}
if (ulStatus & USB_OTG_INTSRCR_SESSREQ)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_SESSREQ;
USB_DBG("ISR:SESSREQ\n");
}
if (ulStatus & USB_OTG_INTSRCR_VBUSERR)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_VBUSERR;
USB_DBG("ISR:VBUS ERROR\n");
}
if (ulStatus & USB_OTG_INTSRCR_CONN)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_CONN;
g_USBConnected = 1;
USB_DBG("ISR:Device Connected\n");
}
if (ulStatus & USB_OTG_INTSRCR_RESET)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_RESET;
USB_DBG("ISR:Signaling the bus reset\n");
}
if (ulStatus & USB_OTG_INTSRCR_EP0)
{
USB_DBG("ISR:Endpoint\n");
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_EP0;
if (USB_OTG->CSR & 0x00000001)
{
printf("HOST_CSR0 = 0x%08x\n",*(unsigned short *)0x01E00412);
printf("RxPktRdy is Set\n");
for (int i = 0;i < RxIdx;i++)
{
RxFIFO[i] = *(unsigned int *)&USB_OTG->FIFO0;
printf("%02x ",RxFIFO[i]);
}
printf("\n");
}
USB_OTG->CSR &= ~0x00000001;
}
if (ulStatus & USB_OTG_INTSRCR_SOF)
{
USB_OTG->INTCLRR |= USB_OTG_INTSRCR_SOF;
USB_DBG("ISR:SOF\n");
}
if (ulStatus & USB_OTG_INTSRCR_DISCONN)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_DISCONN;
g_USBConnected = 0;
USB_DBG("ISR:Disconnected\n");
}
if (ulStatus & USB_OTG_INTSRCR_SUSPEND)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_SUSPEND;
USB_DBG("ISR:SUSPEND\n");
}
if (ulStatus & USB_OTG_INTSRCR_DRVVBUS)
{
// USB_OTG->INTCLRR |= USB_OTG_INTSRCR_DRVVBUS;
USB_DBG("ISR:DRVVBUS\n");
}
USB_OTG->EOIR = 0;//End of Interrupt
}
//////////////////////////////////////////////////////////////////////////////////////
Something Strange happend as follow.
1).After the initialize step,I set the bit RESET of POWER, in order to trigger a reset signal on the USB bus,keep 30ms,and then Clear this bit.As normal,this action will trigger a RESET interrupt,but it doesn't,it triggers a SOF interrupt instead.(others actions,such as force the controller into SUSPEND mode,and the Resume,it doesn't trigger SUSPEND and Resume interrupts)
2).Then I remove the USB device from the mini-USB connector,it doesn't trigger the Disconnect interrupt anymore.
3).if I put Some data(such as the 8byte SETUP Packet that used during device enumeration) into the FIFO0,and the Set the SETUPPKT bit and the TXPKTRDY bit of the HOST_CSR0 register to Start the Control transaction.As normal,it will trigger endpoint interrupt,but nothing happend.(if disable the SOF interrupt(CLEAR the bit SOR of INTRUSBE) at the initialize step,then act this step,it will trigger a Endpoint0 interrupt,the value of the HOST_CSR0 is 0x00000200,that means that the DATATOG bit is set,as normal,when the host send a Get_DeviceDescption packet to the Device,the device will acks something to the host,but the RXPKTRDY bit of the HOST_CSR0 register wasn't set,and the value of the COUNT0 register is 0)
What happended?
Any help would be appreciated.