TMS320C6678 DDR3 interface

Bruno,

Routing the DDR3 memory devices on both top and bottom is an acceptable implementation.  I know of multiple designs in production that have this layout.  This can best be accomplished by using buried or blind via stack-ups including those with micro-vias.  The fly-by routing topology must still be met.  All fly-by nets must follow the same basic route and connect to the SDRAMs in the same order and with similar stub lengths.  I believe your second figure will be easier to implement.  DDR3 BGA SDRAMs are not available in mirrored packages like older flat-pack memories were.  The criss-crossing  fly-by routes created by the first diagram will cause difficulties.

1.  The INVERT_CLOCK comment in the note on page 38 of the DDR3 Layout Guidelines SPRABI1A is misleading.  Logically, the clock delay must always be longer than the data strobe delay.  The INVERT_CLOCK feature adds an apparent 1/2 clock length to make sure this is always met.  In the physical layout, you should keep the clock length longer or only slightly shorter than the shortest data strobe length.  INVERT_CLKOUT is still needed even when the Data Strobe and Clock nets are the same length.  Do not swap the P and N of the DDRCLKOUT signal.  The software will not be able to reflect the state of the clock polarity.

2.  There is no minimum skew between SDRAMs and their fly-by routing.  Each byte lane is independently leveled simultaneously.  However all fly-by nets must be length-matched from the controller to each SDRAM.  Routing all of these nets using only micro-vias will be difficult.  I expect that you will need 3 to 4 routing layers plus reference planes both top and bottom to make this work.  I have seen this done elegantly on a blind-via stack-up where there are separate 8-layer stacks top and bottom. 

3.  These impedance decisions are dependent on the preferences of the customer.  We provide the impedances that we have used in our validation.  Whichever you choose, you need to verify it through IBIS simulation.  Techniques like you mention are discussed in the JEDEC UDIMM spec.  It also discusses different impedance strategies for various topologies.

Tom

Hi Tom,

Thank you for your detailed answer. Some clarification could be helpfull for me :

- You explain that " In the physical layout, you should keep the clock length longer or only slightly shorter than the shortest data strobe length"

1) Do you agree that "only slightly shorter" can extend up to 4-to-5 cm , as shwon in the SPRABI1A-table 17, meaning that clock and ADR/CMD bus being shorter than DQ/DQS bus.

Is this correct ?

2) 1) in your above statement,  "clock length" represents the clock length  from the DSP to one DDR chip, and "strobe length" represents the strobe length from DSP to the SAME DDR chip. And this applies to all the 4 chips individually.

Is this correct ?

With best regards,

Bruno

Hi Tom,

In my project, I met a same question. Because of the limitation of PCB layout area, our PCB layout engineer put the 4 DDR3 chips on both Top and Bottom and routed the Fly-By nets like below.

My questions are:

1. For fabrication cost consideration, we just used through hole vias (not contained buried vias or blind vias) as we did normally when putting all the 4 DDR3 chips on the top layer before.

Could this via-stubs damage the signal integrity to hurt the data transfer stability when running at 1066MT/s or 1333MT/s? We have 18 layers and the board thickness is around 2.3mm.

As we did before when all the 4 DDR3 chips are putted on the top layer, we have no buried vias or blind vias and DDR3 can run OK at the 1333MT/s.

2. For ease layout, our PCB engineer changed the chips' order as the figure above. The clock nets are routed to layer 14 firstly and connected to U3 through a via. Then the clock nets are routed to U4 then U2 and U1 finally.

So when using fly-by routing, does the DD3 chips order is critical to follow the ascending byte sequences ?

3. In one word, is this fly-by topology OK which is showed in the figure I attached?

Regards,

Feng