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GPMC_WAIT0 signal conflict

reto hermann
Intellectual 650 points

Hi
we have a AM335x design with a NAND flash and an FPGA . Both devices are connected via GPMC bus with the processor.  The GPMC_WAIT signal is used in the FPGA interface as a handshake signal. In parallel (wired-or) this signal goes to the ready/busy pin of the NAND flash.

When the NAND flash is busy there is conflict situation because no transfer to/from the FPGA is possible during this (long) busy  time. Any attempt to do that results in bus timeout. 

Question: Is it possible to use a NAND flash without connecting the GPMC_WAIT signal to the ready/busy pin ?

Best regards
Reto

  • 0
    TI__Guru**** 393215 points
    Hi Reto,
     
    Ready/Busy is a mandatory signal for the NAND interface. If you want to boot from NAND you have to connect R/B to GPMC_WAIT0. If you don't need to boot from NAND you can connect R/B to GPMC_WAIT1.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 650 points

    Hi Biser,
    thank you for your quick reply. Sorry to bother you again with this topic even though your answer was very clear. As far as I know there are two possibilities for a NAND flash controller to check the status of the NAND flash device:

    a)     using the R/B# pin
    b)     using read status register (70h)

    If this is true I would say that it depends on the controller whether the R/B# pin is used or not. We have made a test with a Linux system. For this test we have disconnected the R/B# pin of the flash. As expected the system does not boot from the NAND flash anymore BUT after booting from SD card the Linux system seems to have no problems to access the flash and we do not see any difference regarding the read/write performance.

    My conclusion of this test is, that the ROM loader obviously uses the R/B# signal whereas the Linux driver seems to use the status register and if this is correct we have solved our conflict because the FPGA is not used during the boot process.

    However in your answer you seem to be very sure about the statement that the R/B# signal should be used. What do you think about the idea of using the GPMC_WAIT0 for the flash during the boot process and then afterwards using it for the FPGA interface?

    Best regards
    Reto

  • 0 in reply to reto hermann
    TI__Guru 58995 points

    I can confirm the AM335x ROM code uses option A described in your previous post, so GPMC_WAIT0 must be connected to the NAND flash if you plan to boot from it.

    There may be a third option.  Most NAND flash devices provide a maximum time required to complete all operations.  Is so, you could wait the maximum time defined by the specific NAND flash before performing the next operation.  This would be the lowest bandwidth option.

    I do not know which option is used by Linux.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Guru**** 393215 points
    Re: " What do you think about the idea of using the GPMC_WAIT0 for the flash during the boot process and then afterwards using it for the FPGA interface?"
     
    Yes, this could be done in combination with the other methods mentioned above, but you will need some external hardware to isolate the NAND R/B pin before using GPMC_WAIT0 to connect to FPGA (NAND R/B pin is an open-drain output).
  • 0 in reply to Biser Gatchev-XID
    Prodigy 30 points

    hi reto

    if possible share ur fpga code for better understanding