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C64x+ Cache L2 vs. L1 Coherency

Alex
Expert 2430 points

I know the DSP handles the cache coherency of its own memory, but what if another master gets involved?

Case in point:  I have an image buffer on-chip in L2 SRAM.  While my kernel routine is busy chewing away at it, I presume chunks of it are being moved (internally) to L1 cache.  When the kernel routine it finished, I use EDMA to transfer this now modified image buffer to DDR.  Do I need to need to issue a cache writeback to the buffer in L2 space before I begin the EDMA transaction to make sure L2 has a non-dirty copy?

 

Edit:  This is on a C6474.

  • 0
    Expert 1810 points

    The L2 controller keeps track of what is cached in L1D, and will issue a snoop read request to L1 cache when necessary to satisfy a request from outside the DSP core megamodule (such as an EDMA transaction reading from the L2 RAM space).  This is discussed in TI document SPRU871 -- at least in SPRU871K, it is in section 4.3.8.1.

  • 0 in reply to Michael P
    Expert 2430 points

    Thanks for the confirmation and the reference.  Section 4.3.8.5 addressed my question precisely.

  • 0 in reply to Alex
    Expert 2430 points

    Oh, a follow-up question (to anyone).  The megamodule document refers to DMA accesses, but what about SRIO accesses?  The SRIO technical documentation is a little murky on the subject of it using EDMA or its own memory controller, but it does cite it as a memory master.

    So extending my above example, if after DSP0/Core0 is done processing the on-chip memory buffer I transfer that buffer to another DSP via SRIO, do I then need to refresh L2 (via a cache writeback call) before I have SRIO begin transferring the buffer?

  • 0 in reply to Alex
    Expert 1810 points

    I am pretty sure that by "DMA accesses" the document means any access initiated from outside the megamodule.  See, for example, the labels "MDMA" and "SDMA" in Figure 1-1 of SPRU871.  I think it would be possible for the EMC or L2 block to distinguish between EDMA and SRIO initators based on the request metadata, but there would be no good reason to do so.

    By luck, I have tested the behavior you ask about, and the DSP core did not need to write back its dirty cache lines.  I saw the modified-in-L1 values when I performed SRIO NREAD operations from L2 RAM when the target core had a dirty cache line for the read address in its L1D cache.

  • 0 in reply to Michael P
    Expert 2430 points

    Thanks, again, for the verification!