AM1808's McASP with the TDM transfer mode (I2S) is connected to the FPGA.
Sync signals are outputted by the FPGA.
FPGA may stop the output signals between data transfers.
If the ACLKX/R pin is used as the bit clock input, can the bit clock be stopped?
If the AHCLKX/R pin is used as the high-frequency clock input and the ACLKX/R pin is not used, can the high-frequency clock be stopped?
Best regards,
Daisuke
