Hi Community member,
Please let me confirm my understanding for the reason of system configuration just in case.
When use the AIC3204 on EVM/eZdsp, this device will configure as master of I2S.
The reason for this configuration why if the device configure as slave, the DSP(Master) should change the master CLK depending on the sampling rate.
At this time, the DSP will stop and should be done "PLL Bypass" in order to change the PLL.
So, this is not acceptable for user to use this.
Is my understanding correct?
If you have any questions, please let me know.
Best regards.
Kaka