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2 DMA transfers collision

Jiří Babka
Intellectual 465 points

Hello!

Could you help me with the following problem please?

I use the C6748 device. I have 2 EDMA3 transfers:

First transfer is done by Channel Controller 0 (Transfer Controller 0 - EDMA3_0_TC0). It transfers 16 bytes from SPI to internal RAM periodically every 80 microseconds. These are the data from AD converter.

Second transfer is done by Channel Controller 1 (EDMA3_1_TC0). It transfers data (usually 512 B) between DDR and NAND Flash.

Both transfers work fine if they are running alone. But there is the following collision if they are running together: There is periodically performed 1 SPI transfer (2 bytes) and then the SPI transfer is blocked by second transfer for about 50 microseconds. It means that the data from AD converter are missed.

The priorities of Transfer Controllers in Master Priority Register (MSTPRI1) are set so: EDMA3_0_TC0 has the priority 0, EDMA3_1_TC0 has 4.

So the priority of SPI transfer is higher but it gets a fewer time.

How to solve this problem?

Best regards,

Jiri Babka

  • 0
    TI__Guru* 84110 points

    Jiri,

    Does NAND Flash mean MMC/SD port 0 or port 1 or EMIFA?

    Is there a hardware WAIT signal in use that can stall the accesses to the NAND Flash for long time, like 50us? If not, what could happen on the NAND access that would take 50us?

    Are you doing NAND writes or reads, or does the problem show up with either?

    Are you using SPI0 or SPI1?

    My theory is that there is a bottleneck or squeeze point or common port in the path and that too many of the NAND accesses are queued up at that point, which does not allow the SPI access to get through in time to meet the real-time deadline.

    The easiest solution might be to change the programming of the EDMA3_1_TC0 transfer between DDR and NAND Flash so that it transfers fewer bytes at a time and instead does several smaller transfers to eventually add up to 512B total. If constructed correctly, the EDMA3_1_TC0 will send a small burst, like 16 bytes, then chain to itself to trigger another transfer of 16 bytes, and so on until the total of 512 bytes is reached.

    If the number of bytes (16 in my example) is not enough to stall the SPI too long, then the problem can be avoided this way. If the first NAND access can take 50us, then this solution would not help as much and some other solution would have to be figured out.

    Regards,
    RandyP