Is there any demo code of SRIO module on Quad-DSPC 8681 PCIe card available?

Yang Gao,

Since I do not have one of these boards, I cannot say for sure. But most board vendors supply a set of example files with the delivery of the board.

Have you looked through the documentation and files that came with your board?

Have you checked the vendor's website for support files?

Regards,
RandyP

Yang,

I do not have a board here either or example code, but you should be able to use the MCSDK SRIO examples on this PCIe board.  The following items will have to be addressed:

- You will have to take the example out of loopback

- You will have to modify the Serdes configuration for a 250Mhz reference clock on the PCIe card  instead of the 312.5 reference clock on the EVM.

- Make sure the port width is 1X and that you are using the correct port numbers when trying to talk to adjacent DSPs on the PCIe card.

http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html

After installing look at: C:\ti\pdk_C6678_x_x_x_x\packages\ti\drv\srio for the examples.

Regards,

Travis

Yang,

BTW, the file you will need to edit is C:\ti\pdk_C6678_1_1_2_5\packages\ti\drv\srio\device\device_srio_loopback.c

 /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetLoopbackMode(hSrio, 0);
    CSL_SRIO_SetLoopbackMode(hSrio, 1);
    CSL_SRIO_SetLoopbackMode(hSrio, 2);
    CSL_SRIO_SetLoopbackMode(hSrio, 3);

change to:

    /* Configure SRIO ports to operate in loopback mode. */
    CSL_SRIO_SetNormalMode(hSrio, 0);
    CSL_SRIO_SetNormalMode(hSrio, 1);
    CSL_SRIO_SetNormalMode(hSrio, 2);
    CSL_SRIO_SetNormalMode(hSrio, 3);

    /* Configure the SRIO SERDES Receive Configuration. */
    CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (1, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (2, 0x00440495);
    CSL_BootCfgSetSRIOSERDESRxConfig (3, 0x00440495);

    /* Configure the SRIO SERDES Transmit Configuration. */
    CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (1, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (2, 0x00180795);
    CSL_BootCfgSetSRIOSERDESTxConfig (3, 0x00180795);

needs to be adjusted based on Table 3-7 of: http://www.ti.com/lit/ug/sprugw1b/sprugw1b.pdf

This should be good for 1x port config:

    /* Configure the path mode for the ports. */
    for(i = 0; i < 4; i++)
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);

Regards,

Travis

Hi Travis,

Thank you for your reply.

I am going to try that and I would let you know what happened then.

Thanks,

-Yang

Hi,Travis:

1.

As to what you said above :

- Make sure the port width is 1X and that you are using the correct port numbers when trying to talk to adjacent DSPs on the PCIe card.

I agree with you.Because on DSPC8681E DSP0 only use one lane(assume it is lane0) to connect DSP1.

Meanwhile,DSP0 use lane1 to connect DSP3.like below:

   DSP3<--------lane1----->  DSP0  <-----lane0----->DSP1 (Assume it is true as I don't have schematics of 8681

from advantech).

So,Does what I say above mean the same thing with what you said "Make sure that port width is 1x"?

Or,May I ask you the question why you said that Make sure that port width is 1x ? Why cannot we set port

width is 4x? What's your reason?  Is your reason the same with my reason I mention above? If not what's it?

2.

If it's true that we only can use one lane or one port 1x to transfer data from DSP0 to DSP1.

How can I config the port?  I still refer to what you advise :

This should be good for 1x port config:

    /* Configure the path mode for the ports. */
    for(i = 0; i < 4; i++)
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);

I don't understand why you advise that ?

Since we only use one lane or one port 1x to transfer data from DSP0 to DSP1.Does it

need to set for(i=0;i<4;i++) ? I think that should be changed like this:

for(i=0;i<1;i++)   Because you only can use one port or one lane.
I guess we cannot config SRIO  one port 4x mode. Is it true? I don't know ?

Thanks!

Hi,Travis:

About the CSL_SRIO_SetPLMPortPathControlMode,I want to say more .

I run the example in the pdk1.1.2.5 for SRIO Throughput on DSPC-8681E.Although

I have passed the test and the result give the performance.But I cannot understand

why I can pass the test.By the way,I modify some obvious places such as from loopback

to Normal (device to device ) and make example suitable for DSPC 8681E to move

data between DSP0 and DSP1.Luckily, I load consumer out to DSP0 and load producer

out to DSP1 and run successfully. But I don't know why?It seems unreasonable .

1.

I note that pathmode = 4 in the example,it means that you can config full lane for transfer.

pathmode = 4;   //means that one port 4x

for(i = 0; i < 4; i++)
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, pathmode);

But why such config can work successfully? I don't think you can config the SRIO

for one port 4x mode on DSPC-8681E.As I know,DSP0(c6678) has 4 lanes .But

in 8681 DSP0 only use one lane to connect DSP1 and use another lane to connect

DSP3.I am not sure DSP0 and DSP1 use lane0 or lane1 or lane2 or lane3.So do DSP0

and DSP3.But one thing is sure that the lane number which DSP0 and DSP1 connect with

cannot be four.Because DSP0 only have four lanes,the four lanes may be used for DSP1 and

DSP3.But four lanes of DSP0 cannot totally be used by DSP1.So,I believe that you cannot

CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 4) to  set all the ports.Because DSP0 and

DSP1 cannot use all the lanes for transfer. Transfer Pair (DSP0-DSP1) and Transfer Pair (DSP0-DSP3)

will share all the four lanes.Anyhow,I don't believe you can set pathmode = 4.

       In fact ,such config pass the SRIO test .So why?

2.

Another hand,I try to modify pathmode = 0. it meas that four 1x ports.

I believe pathmode = 0 should be suitable and wright.Still the reason I confirm above that

DSP0 and DSP1 only connect each other with one lane,Assume it is lane0.So pathmode =0.

At least it should be 1x port not 4x port.But the result is disappointed.When I modify code like below

for(i = 0; i < 4; i++)
        CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);

The example cannot pass the test.So, Where make mistakes? Does my guess standup?

Where can I get the schematics of DSPC-8681E,So I can know how many lanes and which lanes

do DSP0 and DSP1 use .So I can config SRIO port correctly .How to treat this problem?

Who leads the bad result?

Best Regards!

David,

Sorry for the late reply, still catching up on some of the items that came in during the holidays...

David George said:

So,Does what I say above mean the same thing with what you said "Make sure that port width is 1x"?

Or,May I ask you the question why you said that Make sure that port width is 1x ? Why cannot we set port

width is 4x? What's your reason?  Is your reason the same with my reason I mention above? If not what's it?

Yes, it must be in 1X mode, there is physically only one TX differential pair and one RX differential pair routed between each DSP, so it only supports 1X mode.  For 4X mode, all 4 RX and 4 TX differential pairs would have to be routed between the two link partner devices.

It may be helpful to look at Table 2-4 in http://www.ti.com/lit/ug/sprugw1b/sprugw1b.pdf.  We only support Configuration 4, but all modes within that configuration are supported.

David George said:

Since we only use one lane or one port 1x to transfer data from DSP0 to DSP1.Does it

need to set for(i=0;i<4;i++) ? I think that should be changed like this:

for(i=0;i<1;i++)   Because you only can use one port or one lane.
I guess we cannot config SRIO  one port 4x mode. Is it true? I don't know ?

Yes you really only need to write one register, although this register can be addressed on a per-port basis, there is only one register per path/configuration.

regards,

Travis