• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 98 subscribers
  • Views 378 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

About 32/34bit address on C6678 srio

David Yang1
Intellectual 435 points

Hi,Ti guys,

I am using the Keystone_srio example from the forum on c6678 srio trying to connect a c6678 to a V6 FPGA with srio core v5.6. My co-worker told me that fpga might need a 34bit address. But Dsp use 32 bit address in default. From the sprugw1a I find little discription about 34 bit address, just a PE_LL_CTL regsiter, and in the example project, the PE_LL_CTL has already been set to support 34 bit address. What alse should I do if I want to send&rec 34bit address packet? Shall I just fill the LSU_REG0 RapidIO MSB field with the higher 2bits when I send a packet? And as to recieve, how shall I config the chip? How will DSP srio deal with a 34 bit address(the higher 2bit is 0, only 32 effective bit ,but in 34 bit format) when all the local address is 32 bit?

Thanks!

David Yang

  • 0
    TI__Guru* 84110 points

    David,

    For details on the SRIO standard and how the signalling is performed between two devices, you will find the most useful information at rapidio.org for the version of SRIO that the C6678 supports, version 2.1.

    If the FPGA supports that same specification level, then you will be able to communicate between the two devices.

    You can look at the SRIO example projects to see how the extra address bit fields are filled and used on the C6678 side. This should answer many of your questions. Setting the top two bits to 0 is probably the most common thing to do for the DSP side. If there is a need to use those bits other than 0 on the FPGA side, you will have that capability.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 435 points

    Hi, RandyJ,

    Thank you for your answer! And can you give me some advise on SRIO example projects? Because the Keystonez-Srio project I get from the forum just set the  LSU_REG0 RapidIO MSB field to 0. When can I find the example that actually use the ectra address? Or just like I supposed, set  the PE_LL_CTL to enable 34bit capability and fill the LSU_REG0 RapidIO MSB with the higher extra 2bit? Our fpga's srio is still not able to work all right, so I can't verify from my side.Thanks for your time! 

    David Yang

     

  • 0 in reply to David Yang1
    TI__Guru* 84110 points

    David,

    Your solutions sounds correct. I doubt we have any example code for more than 32-bits because we do not often work with devices that require more than 32 bits.

    You may be misled by your co-worker's statement, and you may not need to set any of those extra bits to 1, just need to recognize that they exist already.

    Or you will need to debug the FPGA design or connect an SRIO bus analyzer test equipment onto the SRIO line to determine if the right information is being sent by the DSP.

    The easiest place to start debugging would be to connect two DSP EVM boards together or to find a way to loopback the SRIO cable to the same DSP EVM board, then see if the code works there. If so, then you have confidence that small changes will be okay and that you should be ready to debug on the FPGA.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 435 points

    Hi,RandyP

    Thanks for your answers, that do help a lot! Before I test NO_LOOPBACK with Fpga, I already succeedded in DSP&Fpga external_line loopback(DSP as master), and 2Dsp NO_LOOP_BACK test, with or without doorbell.So that means, as you advised, the code works.

    Thanks again!

    Regards,

    David Yang