My latest AM3352 project is not coming out of reset. I see WARMRST_L (or nRESETIN_OUT) being driven low by the processor. Power on Reset (POR) is high. Looking at these signals with a scope, I see that while POR is low, WARMRST_L pops high for about 4 ms, then goes low about 2 ms before POR goes high. WARMRST_L remains low forever.
I have verified all of the power rails to the AM3352 are correct, plus all of the other signals are healthy.
Looking at the Tech Ref Manual, there is the list of events that can cause WARMRST_L to be asserted by the AM3352, I'm not sure that any of them explain what I am seeing ... If, say, there was a SW warm reset event, I would not expect that to happen so quickly after POR goes high. Same applies for an emulation reset or any other reset requestor.
This new project's AM3352 section is almost identical to my last AM3352 design which worked fine. Thre are only minor differences, mostly related to the UARTS and i2c port usage. That makes this problem frustrating - it Should work. It is based on a known good design.
Any tips or suggestions would be greatly appreciated.
-Fraser.
