about deciding the round trip board delay on AM1806 DDR I/F

RY

Is 10ns your board delay?

Besides the board delay, what is your CAS latenyc?

The programmed value = CL to CL+2

Thanks
David

David-san,

Thank you so much for your reply.
10nsec is just assuming.
Because this design is for our customer's.

And sorry, also I don't know their CAS Latency of DDR.
But, I think that the calculation is below if assuming CL=2:
  RL field = CL + round trip board delay - 1 = 2 + round trip board delay - 1

It is OK that it is assumed CL=2.
If it round trip boad delay is calculated as 1.5, what value should I set?

  RL field = CL + round trip board delay - 1 = 2 + 1.5 -1 = ?? (actual value is integer)

And, then:

Is it allowed that I set RL field as value with the margin further than the actual value?

Best regards, RY

RY

Minimum RL = CL and Maximum RL = CL+2. In the case CL=2, then minimum RL = 2, and maximum RL = 4. if round trip board delay is 1.5, then RL = 2+1.5 -1=3. So you can use value of 2, 3, or 4 for RL, but do not exceed the value of 4 as this will cause performance issue.

Thanks

David 

David-san.

Sorry. I can not understand your answer.
Because it seems to be different between your answer and description of TRM.

This is quote from TRM(spruh83a P336):
  The minimum RL value is CAS latency plus 1 and the maximum RL value is CAS latency plus 2

Which is correct?
  a) Your answer : Minimum RL = CL   and Maximum RL = CL+2.
  b) TRM         : Minimux RL = CL+1 and Maximum RL = CL+2.

And,

David (ASIC) Liu said:

but do not exceed the value of 4 as this will cause performance issue.

What is mean the performance issue?
Is it mean that the data will corrupt?

Best regards, RY

RY

For DDR2, the required DDR PHY read latency = CL+1 to CL+3. The programmed value in the register must be minus one the required value. Therefore, programmed value = CL to CL+2.

For mDDR, the required DDR PHY read latency = CL+2 to CL+3. The programmed value in the register must be minus one the required value. Therefore, programmed value = CL+1 to CL+2.

When data goes from AM1806 to DDR, it basically synchronizes the data from AM1806 clock domain to DDR clock domain. To determine the point at which the data can be reliably resynchronized, you need to calculate the minimum and maximum round-trip delay. Exceed this value can cause data not being synchronized correctly.

Thanks
David

David-san,

I am sorry for my late reply.
Thank you so much for your answer.

I understand that:
  a) For DDR2 : Minimum RL = CL   and Maximum RL = CL+2.
  b) For mDDR : Minimux RL = CL+1 and Maximum RL = CL+2.

But, I think it should be described in TRM.
Would you consider updating it when you release new TRM?

David (ASIC) Liu said:

When data goes from AM1806 to DDR, it basically synchronizes the data from AM1806 clock domain to DDR clock domain. To determine the point at which the data can be reliably resynchronized, you need to calculate the minimum and maximum round-trip delay. Exceed this value can cause data not being synchronized correctly.

Thank you very much for your comment.
I am concerning how can I get the reliability on our system.

 - Can I think that the data is missed if synchronizing is failed?
   Or, does it have just penalty of access speed?

 - How can I calculate round-trip delay accurately?
   The generally comment is very helpful for me.
   Because, I think it is difficult to measure the round trip delay time.

Best regards, RY