Hello.
Although it is not supported ODT on AM1806 DDR controller, there is T_ODT field on SDTIMR2 register.
On trm(spruh83a: P344) Table 14-28 describes that:
T_ODT :
Specifies the minimum number of DDR_CLK cycles from ODT enable to write data driven for DDR2 SDRAM.
T_ODT must be equal to (CAS latency - tAOND -1). T_ODT must be less than CAS latency minus 1.
This feature is not supported because the DDR_ODT signal is not pinned out.
What value should I set to this field? (CAS latency - tAOND -1?, or no effect because ODT is not supported?)
Best regards, RY
