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What are the compulsory signals for external video sync?

Jemish Patel
Intellectual 740 points


Hi all,

We are using DM8148 in our project. In processor VIN0 port has all the signal available for external sync (HSYNC, VSYNC, CLOCK, DE, FLD). But on VIN1 port we have (HSYNC, VSYNC, CLOCK) are available but DE and FLD are muxed on same pin(AA23). Are DE and FLD signals both are necessary for external video sync? What is significance of this both signal? What may be problem if DE and FLD are muxed ?

Regards,

Jemish

  • 0
    TI__Guru**** 481755 points

    Hi Jemish,

    FLD signal is required only if you have interlaced input. So below combination should work

    if you have interlaced input

    HSYNC + VSYNC + FLD + CLK

    if you dont have interlaced input

    VSYNC + DE + CLK

    Regards,

    Brijesh Jadav

  • 0 in reply to Brijesh Jadav
    Intellectual 740 points

    Hi Brijesh,

    We have HDMI receiver IC communicating with VIN1 port of DM8148. Output signals of our decoder chip are ( HSYNC + VSYNC/FLD (muxed on one pin) + DE + CLK ) . As we have VSYNC and FLD muxed on one pin it doesn't seem like above mention combinations useful for us.

    Regards,

    Jemish

  • 0 in reply to Jemish Patel
    TI__Guru**** 481755 points

    Hi Jemish,

    vsync is basic requirement, it is used to mark start of the frame, so you have to use vsync. Since you cannot anyway use FLD output from your chip, you have to use pin AA23 as DE.

    Now regarding interlaced input, if you have requirement for the interlaced input, you have to detect the field detection by hsync skew.


    So you could use Vsync + Hsync + CLK for all kind of input modes.. 

    Regards,

    Brijesh Jadav

  • 0 in reply to Brijesh Jadav
    Intellectual 740 points

    Hi Brijesh,

    Thanks for your reply. Our confusion is clear now.  If we have interlace video on VIN1 port , how to identify it? Would please elaborate "field detection by hsync skew" . It will be very helpful for us.

    Regards,

    Jemish

  • 0 in reply to Jemish Patel
    TI__Guru**** 481755 points

    Hi Jemish,

    Field can also be detected by vsync/hsync skew. In this method, if vsync and hsync are aligned exactly, it will treated as even field, otherwise it is odd field. Input port supports this method of interlaced mode, but you will check in your decoder if it can support this method for interlaced output.

    Regards,

    Brijesh Jadav