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hyperlink - C6670

Dear support,

We have our own designed boards using 2*C6670. The DSPs are connected using hyperlink and I am using the provided example to validate our hardware. I have a few simple questions.

1) On the C6670, the hyperlink example should provide token passing between 2 endpoints using EDMA or CPU IO. Only the second solution is implemented. Do you know if there was a problem using hyperlink with EDMA? Is this solution implemented on other platforms?

2) Running the default set up with hyplnk_EXAMPLE_SERRATE_10p000 works perfectly well, Running hyplnk_EXAMPLE_SERRATE_12p500 provides the following warnings "Remote after passing tokens WARNING: ECCErrors.sglErrCor = 1725" where signal integrity issues were detected but corrected. So here are my questions:

a) was the example tested at 12.5 GBps and was the signal integrity correct?

b) Each loop provides this amount of detected and corrected errors, is there published recommendation on how to improve the link?

3) finally, the example states the following "Link Speed is 4 * 12.5 Gbps - Passed 65536 tokens round trip (read+write through hyplnk) in 15960 Mcycles - Approximately 243540 cycles per round-trip. Does that mean that 4096 byes were written and read back in 243540 cycles?

Thanks in advance

Aymeric

  • Hi Aymeric,

    According to Advisory 22 of the C6670 Errata document, 

    "The HyperLink interface is currently limited to a maximum transfer rate of 10Gbaud/s 

    per lane (40Gbaud/s for four lanes) due to SerDes PLL limitation."

    Regards, Bill

  • Thanks Bill, one down...

  • aymeric dupont said:
    1) On the C6670, the hyperlink example should provide token passing between 2 endpoints using EDMA or CPU IO. Only the second solution is implemented. Do you know if there was a problem using hyperlink with EDMA? Is this solution implemented on other platforms?

    All of our throughput measurements used EDMA, and no problems using EDMA were found.  The reason this isn't in the example, is because the example is intended to be as simple as possible, focusing on hyperlink, not EDMA usage.

    aymeric dupont said:
    3) finally, the example states the following "Link Speed is 4 * 12.5 Gbps - Passed 65536 tokens round trip (read+write through hyplnk) in 15960 Mcycles - Approximately 243540 cycles per round-trip. Does that mean that 4096 byes were written and read back in 243540 cycles?

    Please don't try to use the cycle count as a throughput measurement as indicated by the example itself. 

  • Hi John,

    Just now seen your post and got surprised, as till now I'm calculating my Hyperlink throughput using cycle count and getting very bad result 303Mbps.

    My Project is a single card and have two TI DSP C6674 and on board hyperlink interface configured with 156.25MHz clock, 4 lanes and lane rate is 6.25Gbps.

    So expected is 6.25Gpbs theoretically but getting just 303Mbps by calculating using CPU Cycles.

    Request you to tell how to measure throughput without Cycle count and any suggestions about my problem of very low throughput observation (I'm running TI  example code by modifying data transfer to 400MB)

    Awaiting for your inputs.

    Thanks

    Mani Kumar

  • I have answered the same question on your new post.
    e2e.ti.com/.../1467912

    Thanks,