AM335x with Davicom RMII on EVM

1. What do you mean when you say you "replaced the original"? Did you mod an EVM to support this PHY, or is this a custom design?
2. Can you read/write the PHY registers via MDIO?

Hi DK:

Thanks for your response.

For your question:

1. We mod an EVM to support this phy

2. Phy register CAN be read/write via MDIO and I also see the auto-negotiation done.

Besides, I also modify the pin mux setting in uboot and linux kernel as below  (ti-sdk-am335x-evm-05.06.00.00)

1. In U-Boot, board/ti/am335x/mux.c I add a pin mux rmii1_pin_mux based on rgmii1_pin_mux as below

static struct module_pin_mux rmii1_pin_mux[] = {
{OFFSET(mii1_col), MODE(3) | RXACTIVE | PULLUDEN}, /* MII1_COL */
{OFFSET(mii1_crs), MODE(1)| RXACTIVE}, /* MII1_CRS */
{OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(1)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(3) }, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(3) | RXACTIVE}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(3)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(1)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(1)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(1) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(1) }, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(1) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(1) }, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};

and change configure_module_pin_mux(rgmii1_pin_mux)  to configure_module_pin_mux(rmii1_pin_mux)

2. In linux kernel, arch/arm/mach-omap2/board-am335xevm.c

I change the data in  struct evm_dev_cfg gen_purp_evm_dev_cfg[] 

from {rgmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL},  to  {rmii1_init, DEV_ON_BASEBOARD, PROFILE_ALL}, 

But after measure the tx_en and td1, I can not measure any signal output. :(

Thanks a lot 

Your DM9162 RMII PHY should be connected to the following AM335x terminals.

The DM9162 RXD[1:0] terminals should be connected to the AM335x MII_RXD[1:0] terminals configured for pin multiplex mode (1) | RXACTIVE.

The DM9162 TXD[1:0] terminals should be connected to the AM335x MII_TXD[1:0] terminals configured for pin multiplex mode (1).

The DM9162 TXEN terminal should be connected to the AM335x MII_TX_EN terminal configured for pin multiplex mode (1).

The DM9162 RXDV terminal should be connected to the AM335x MII_CRS terminal configured for pin multiplex mode (1) | RXACTIVE.

The DM9162 MDC terminal should be connected to the AM335x MDC terminal configured for pin multiplex mode (0) | RXACTIVE | PULLUP_EN.

The DM9162 MDIO terminal should be connected to the AM335x MDIO terminal configured for pin multiplex mode (0) | RXACTIVE | PULLUP_EN.

I assume you plan to use a 25MHz crystal on the DM9162 and use the 50MHz output from the the DM9162 to source the AM335x RMII1_REF_CLK terminal.  This terminal will need to be configured for pin multiplex mode (0) | RXACTIVE.

The internal AM335x and DM9162 pull-up/pull-down resistors may effect the logic voltage applied to the respective DM9162 inputs that configure the PHY on the rising edge of reset.  So it may be necessary to use external resistors to over-drive the AM335x internal resistors if the PHY reset is connected to the AM335x PWRONRSTn or the application software may need to disable the AM335x internal resistors before it releases the PHY reset if it is controlled by one of the AM335x GPIOs.

Regards,
Paul

Hi Peaves:

Thanks for your response.

I already done this and still not see any output from tx_en and tx_0

I set pin mux both in u-boot and linux kernel

below is the value I read back 

[ 1.373413] omap_mux_init_signal: Setting signal mii1_crs.rmii1_crs_dv 0x0021 -> 0x0021
[ 1.381805] omap_mux_init_signal: Setting signal mii1_rxerr.rmii1_rxerr 0x0021 -> 0x0021
[ 1.390289] omap_mux_init_signal: Setting signal mii1_txen.rmii1_txen 0x0001 -> 0x0001
[ 1.398559] omap_mux_init_signal: Setting signal mii1_txd1.rmii1_txd1 0x0001 -> 0x0001
[ 1.406829] omap_mux_init_signal: Setting signal mii1_txd0.rmii1_txd0 0x0001 -> 0x0001
[ 1.415069] omap_mux_init_signal: Setting signal mii1_rxd1.rmii1_rxd1 0x0021 -> 0x0021
[ 1.423339] omap_mux_init_signal: Setting signal mii1_rxd0.rmii1_rxd0 0x0021 -> 0x0021
[ 1.431610] omap_mux_init_signal: Setting signal rmii1_refclk.rmii1_refclk 0x0020 -> 0x0020
[ 1.440338] omap_mux_init_signal: Setting signal mdio_data.mdio_data 0x0030 -> 0x0030
[ 1.448516] omap_mux_init_signal: Setting signal mdio_clk.mdio_clk 0x0030 -> 0x0030

It looks like the value are both the same in u-boot and linux kernel.

I also read back the gmii_sel and it is 0xC5 as I expected. 

The MDIO_CLK/MDIO_DATA/ have signal and the phy also output 50Mhz signal correct too.

Do you have any idea or experience ?  Thanks