Hi!
I'm trying to output 768x576 video via VPBE on dm368
Here is how I config regs:
unsigned int temp = 0;
void __iomem *pinmux1 = (void __iomem *) IO_ADDRESS(0x01C40004);
temp = __raw_readl(pinmux1); //select VCLKL and HVSYNC
temp &= ~(0x01 << 22); //VCLK Enable
__raw_writel(temp, pinmux1);
__raw_writel(0x38, IO_ADDRESS(SYS_VPSS_CLKCTL)); //clock configured for 29.5 Mhz
dispc_reg_out(VENC_OSDCLK0, 1);
dispc_reg_out(VENC_OSDCLK1, 2);
dispc_reg_out(VENC_DACTST, 0x0);
//YCC8 BT.656
dispc_reg_out(VENC_CLKCTL, 0x11);
//OSD Set
__raw_writel(mode_info->left_margin, IO_ADDRESS(DM365_OSD_REG_BASE + OSD_BASEPX));
__raw_writel(mode_info->upper_margin + 2, IO_ADDRESS(DM365_OSD_REG_BASE + OSD_BASEPY));
dispc_reg_out(VENC_VIDCTL, 0x6000);
dispc_reg_out(VENC_DCLKCTL, 0x005);
dispc_reg_out(VENC_DCLKPTN0, 0x13);
dispc_reg_out(VENC_SYNCCTL, 0x400F);
dispc_reg_out(VENC_VMOD, 0x1251);
dispc_reg_out(VENC_YCCCTL, 0x1);
dispc_reg_out(VENC_VDPRO, 0x100);
dispc_reg_out(VENC_HINT, 0x75F);
dispc_reg_out(VENC_HSTART, 0x15C);
dispc_reg_out(VENC_HVALID, 0x600);
dispc_reg_out(VENC_VINT, 0x271);
dispc_reg_out(VENC_VSTART, 0x18);
dispc_reg_out(VENC_VVALID, 0x120);
I captured data with logic analyzer and discovered that field bit in SAV/EAV code are always zero. But it must be equal zero for 288 lines+vertical blanking and must be equal 1 for another part of frame. Please help, what am I doing wrong?
Here is what I captured:
non-standart 768x576 digital output:
standart pal 720x576 digital output(works fine):