• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 101 subscribers
  • Views 588 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6678 PCIe Bus Enumeration

fearghal rudden
Intellectual 480 points
Other Parts Discussed in Thread: TMS320C6678

Hi,

I have been having problems when trying to enumerate the PCIe bus on a design I have interfacing a Xilinx Virtex 7 FPGA and the TMS320C6678.

The PCIe link is up and running but when I try to enumerate the bus I get the following results:

Start Enumeration of PCIe Fabric on This System

PCI: found device at : 0:0:0
PCI: device info is DEADBEEF
PCI: no device found at : 0:1:0
PCI: no device found at : 0:2:0
            |             |
PCI: no device found at : 0:31:0

PCI: found device at : 1:0:0
PCI: device info is DEADBEEF
PCI: found device at : 1:1:0
PCI: device info is DEADBEEF
PCI: found device at : 1:2:0
PCI: device info is DEADBEEF
            |             |
PCI: found device at : 7:30:0
PCI: device info is DEADBEEF
PCI: found device at : 7:31:0
PCI: device info is DEADBEEF

As you can see I find a device, DEADBEEF, on Bus 0 at Device number 0 and with Function 0. This is the root complex of my design.

When continuing to scan through other devices on Bus 0, I do not find the C6678 which I had hoped. Then when scanning through device numbers 0 to 31 on Bus 1 - Bus 7, I find my root complex device at every device addressed. Would you know what could cause this issue?

I have changed the bus numbering as follows when running my test: (Primary: 0, Secondary: 1, Sub: 2), (Primary: 0, Secondary: 1, Sub: 1), (Primary: 0, Secondary: 0, Sub: 0) but I get the same results.

Would you have a reference design for AXI to PCIe for a Virtex 7 device? Even something that is unsupported by you if at all possible.

Thank you,

Fearghal

  • 0
    TI__Genius 12065 points

    Fearghal,

    Which operation mode (Root Complex (RC) / Endpoint (EP)) do you configure the FPGA and C6678 PCIe module please?

    Do you have the third PCIe module as RC in your system or one of the FPGA and C6678 PCIe module is configured as RC please?

    If there is only one RC and one EP in your design, I am wondering why you need to enumerate the bus since the enumeration is not necessary for this peer-to-peer setup.

    If you have single RC and multiple EPs in your design, do you have any OS with the bus enumeration software running on RC please?

    Could you elaborate how "the PCIe link is up and running" in your system please? 

  • 0 in reply to Steven Ji
    Intellectual 480 points

    Hi Steven,

    The FPGA is configured as Root Complex and the C6678 is configured as end point. There are no other modules in the system. Even though enumeration is not necessary in this peer-to-peer setup, should I not still be able to find the C6678 when I scan all the buses?

    When saying the link is up, I was only indicating that I can see communication on the lines when I probe them with an oscilloscope and that a link is detected between the FPGA and the C6678. I shouldn't have highlighted it.

    Regards,

    Fearghal

  • 0 in reply to fearghal rudden
    Intellectual 480 points

    Hi Steven,

    We solved the issue in-house. The problem we were experiencing was due to the PCIe core we were using on the FPGA. Thanks for following up on this and assisting me with it.

    Best Regards,

    Fearghal