Hi,everyone
I'm trying to connect my 6678EVM to FPGA by EMIF16(CPU clock is 1GHz,so EMIF16 clock is about 166.7MHz)and I met a problem.
The I/O on 6678EVM board is 1.8V and I have to changle it to 3.3V considering FPGA's voltage requirement.
Someone suggests me to use a pull-up resistor, it seems quite easy but I'm worrying about its performance,what parameters should I consider when doing such level shift?And is it much better to use a level shifter instead of pull-up resistor?
I've found someone else discussing time delay when using a level shifter,but I know little about it,is it quite important when I connect C6678 to FPGA?
I'm not familiar with connecting DSP to other facility = =,Could anyone spare me some time to help me out?I'll be very grateful.
Zhao