Hi All, I have a question about possible reasons of a problem with a USB TX transmission. The USB module is programmed without using the CSL library. Also the CPPI dma is not used. The usb tx routine is very simple and based on the documentation: in loop: 1. loading 512 bytes to the endpoint fifo 2. set the TXPKTRDY bit in the indexed endpoint register 3. wait for the tx ready interrupt The transmission generally works but in some rare cases I don't get the TX ready interrupt and the TXPKTRDY bit is not cleared. While debugging the USB transmission using the usb analyzer I figured out, that sometimes there are invalid "in transactions" (instead of 512 bytes, the packet length is shorter and a CRC error is signaled), after an invalid transaction, I see that there is a re-transmission (the correct packet includes the incomplete data from the invalid transaction). After the correct re-transmission I don't get any problems. But sometimes (while the missing TX ready interrupt) I see that the re-transmission also fails (the packet is also not full length). After This situation, if I reinitialize the USB module I am able to perform a new transfers. After a while situation repeats. I figured out, that the problem frequency is strongly related with the system load. For example if the USB transmitted data is generated in the DSP, the problem appears after a minute. But if there are frequent DMA transmissions on the EMIF bus (data from external source), the USB problem appears quickly (few seconds)
My question is. What shall we focus on while trying to remove the problem. Could it be wrong configuration of the USB module (software) or rather its related with some hardware issues like wrong usb connector, cable, pcb layout.
I'll be thankful for any hint.