It appears that the AM3703 GPMC controller will hang/crash if software writes NAND page data to the GPMC_NAND_DATA register too quickly.
Observations:
- Once the GPMC controller has failed/hung, any attempt to read from the GPMC controller registers (e.g. 0x6e000000, the GPMC_REVISION register) will result in a data-abort exception being triggered in the processor.
- Once the GPMC controller has failed/hung, any attempt to access memory that was previously accessible on any of the GPMC chip-selects will now result in a data-abort exception being triggered in the processor.
- If the NAND GPMC timings are set to be as fast as the connected NAND device allows, only a short delay is required between each write to the GPMC_NAND_DATA register in order to prevent the GPMC controller from failing. If the NAND GPMC timings are set to be slower then a longer delay is required between each write to the GPMC_NAND_DATA register in order to prevent the GPMC controller from failing.
- When the code is modified so that the NAND page data is written to the NAND device using the NAND prefetch engine then the GPMC does not fail, regardless of the length of the configured NAND GPMC timings.
The current workaround will be to go with using the prefetch engine to write the page data.
I would like to understand why the GPMC controller can be made to hang by writing to the GPMC_NAND_DATA register too quickly, how to determine what the correct amount of delay needs to be when writing data repeatedly to the GPMC_NAND_DATA register, and/or if there is a better way to fix this problem.